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ŠKARVADA, J. HERRMAN, T. KOTÁSEK, Z.
Originální název
RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool
Typ
článek ve sborníku ve WoS nebo Scopus
Jazyk
angličtina
Originální abstrakt
The paper presents testability analysis method which is based on partitioning circuit under analysis (CUA) to testable blocks (TBs). A formal approach utilizing the concepts of discrete mathematics is used for this purpose. The partitioning CUA into TBs is further exploited for power consumption optimization during test application. Software tools which were developed during the research and integrated into the third party design tool are also described. Experimental results gained from applying the methodology on selected benchmarks and practical designs are demonstrated.
Klíčová slova
Testable block, power consumption estimation, test vectors generation, power consumption optimization.
Autoři
ŠKARVADA, J.; HERRMAN, T.; KOTÁSEK, Z.
Rok RIV
2007
Vydáno
12. 10. 2007
Nakladatel
Institute of Computing Technology, Chinese Academy of Sciences
Místo
Beijing
Strany od
175
Strany do
181
Strany počet
7
BibTex
@inproceedings{BUT26071, author="Jaroslav {Škarvada} and Tomáš {Herrman} and Zdeněk {Kotásek}", title="RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool", booktitle="IEEE 8th Workshop on RTL and High Level Testing", year="2007", pages="175--181", publisher="Institute of Computing Technology, Chinese Academy of Sciences", address="Beijing" }