Publication detail

Checker Design for On-line Testing of Xilinx FPGA Communication

STRAKA, M. TOBOLA, J. KOTÁSEK, Z.

Original Title

Checker Design for On-line Testing of Xilinx FPGA Communication

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enabling to describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs.

Keywords

Communication Protocol Testing, Fault Tolerant Systems, checker design

Authors

STRAKA, M.; TOBOLA, J.; KOTÁSEK, Z.

RIV year

2007

Released

21. 6. 2007

Publisher

IEEE Computer Society

Location

Rome

ISBN

0-7695-2885-6

Book

The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Pages from

152

Pages to

160

Pages count

9

URL

https://www.fit.vut.cz/research/publication/8353/

BibTex

@inproceedings{BUT28609,
  author="Martin {Straka} and Jiří {Tobola} and Zdeněk {Kotásek}",
  title="Checker Design for On-line Testing of Xilinx FPGA Communication",
  booktitle="The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",
  year="2007",
  pages="152--160",
  publisher="IEEE Computer Society",
  address="Rome",
  isbn="0-7695-2885-6",
  url="https://www.fit.vut.cz/research/publication/8353/"
}

Documents

dft07.pdf