Detail publikace

Checker Design for On-line Testing of Xilinx FPGA Communication

STRAKA, M. TOBOLA, J. KOTÁSEK, Z.

Originální název

Checker Design for On-line Testing of Xilinx FPGA Communication

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enabling to describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs.

Klíčová slova

Communication Protocol Testing, Fault Tolerant Systems, checker design

Autoři

STRAKA, M.; TOBOLA, J.; KOTÁSEK, Z.

Rok RIV

2007

Vydáno

21. 6. 2007

Nakladatel

IEEE Computer Society

Místo

Rome

ISBN

0-7695-2885-6

Kniha

The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Strany od

152

Strany do

160

Strany počet

9

URL

https://www.fit.vut.cz/research/publication/8353/

BibTex

@inproceedings{BUT28609,
  author="Martin {Straka} and Jiří {Tobola} and Zdeněk {Kotásek}",
  title="Checker Design for On-line Testing of Xilinx FPGA Communication",
  booktitle="The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",
  year="2007",
  pages="152--160",
  publisher="IEEE Computer Society",
  address="Rome",
  isbn="0-7695-2885-6",
  url="https://www.fit.vut.cz/research/publication/8353/"
}

Dokumenty

dft07.pdf