Publication detail

Reliability Models for Fault Tolerant Architectures Based on FPGA

STRAKA, M. KOTÁSEK, Z.

Original Title

Reliability Models for Fault Tolerant Architectures Based on FPGA

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In this presentation, a methodology of FTS design based on FPGA is presented. The FT architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the FTS is implemented. Finally, the results of research and the comparison of our approach with classical TMR and duplex architectures for different failure rates are presented.

Keywords

TMR, checker, fault tolerant system, reliability model, availability, FPGA

Authors

STRAKA, M.; KOTÁSEK, Z.

RIV year

2009

Released

15. 10. 2009

Publisher

Faculty of Informatics MU

Location

Brno

ISBN

978-80-87342-04-6

Book

5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

Pages from

239

Pages to

239

Pages count

1

BibTex

@inproceedings{BUT33747,
  author="Martin {Straka} and Zdeněk {Kotásek}",
  title="Reliability Models for Fault Tolerant Architectures Based on FPGA",
  booktitle="5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2009",
  pages="239--239",
  publisher="Faculty of Informatics MU",
  address="Brno",
  isbn="978-80-87342-04-6"
}