Detail publikace

Reliability Models for Fault Tolerant Architectures Based on FPGA

STRAKA, M. KOTÁSEK, Z.

Originální název

Reliability Models for Fault Tolerant Architectures Based on FPGA

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In this presentation, a methodology of FTS design based on FPGA is presented. The FT architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the FTS is implemented. Finally, the results of research and the comparison of our approach with classical TMR and duplex architectures for different failure rates are presented.

Klíčová slova

TMR, checker, fault tolerant system, reliability model, availability, FPGA

Autoři

STRAKA, M.; KOTÁSEK, Z.

Rok RIV

2009

Vydáno

15. 10. 2009

Nakladatel

Faculty of Informatics MU

Místo

Brno

ISBN

978-80-87342-04-6

Kniha

5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

Strany od

239

Strany do

239

Strany počet

1

BibTex

@inproceedings{BUT33747,
  author="Martin {Straka} and Zdeněk {Kotásek}",
  title="Reliability Models for Fault Tolerant Architectures Based on FPGA",
  booktitle="5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2009",
  pages="239--239",
  publisher="Faculty of Informatics MU",
  address="Brno",
  isbn="978-80-87342-04-6"
}