Publication detail

Cache-Based Parallel Particle Rendering Engine

TIŠNOVSKÝ, P. HEROUT, A. ZEMČÍK, P.

Original Title

Cache-Based Parallel Particle Rendering Engine

Type

journal article - other

Language

English

Original Abstract

Current hardware graphics rendering engines efficiently process hugeamount of triangle data, but are not as suitable when operating onpoint-based scenes. This paper presents an architectural design forpoint-based rendering. We are using a previously developed hardwaremodel featuring FPGA, DSP and CAM memory.

Keywords

particle, surfel, particle renderer, particle rendering engine, FieldProgrammable Gate Array - FPGA, Content Addressable Memory - CAM,Digital Signal Processor - DSP, Programmable Switching Matrix - PSM,Configurable Logic Block - CLB, cache, spatial data locality

Authors

TIŠNOVSKÝ, P.; HEROUT, A.; ZEMČÍK, P.

RIV year

2003

Released

22. 9. 2003

ISBN

1213-161X

Periodical

ElectronicsLetters.com - http://www.electronicsletters.com

Year of study

2003

Number

1

State

Czech Republic

Pages count

8

BibTex

@article{BUT42291,
  author="Pavel {Tišnovský} and Adam {Herout} and Pavel {Zemčík}",
  title="Cache-Based Parallel Particle Rendering Engine",
  journal="ElectronicsLetters.com - http://www.electronicsletters.com",
  year="2003",
  volume="2003",
  number="1",
  pages="8",
  issn="1213-161X"
}