Detail publikace

Cache-Based Parallel Particle Rendering Engine

TIŠNOVSKÝ, P. HEROUT, A. ZEMČÍK, P.

Originální název

Cache-Based Parallel Particle Rendering Engine

Typ

článek v časopise - ostatní, Jost

Jazyk

angličtina

Originální abstrakt

Current hardware graphics rendering engines efficiently process huge amount of triangle data, but are not as suitable when operating on point-based scenes. This paper presents an architectural design for point-based rendering. We are using a previously developed hardware model featuring FPGA, DSP and CAM memory.

Klíčová slova

particle, surfel, particle renderer, particle rendering engine, Field Programmable Gate Array - FPGA, Content Addressable Memory - CAM, Digital Signal Processor - DSP, Programmable Switching Matrix - PSM, Configurable Logic Block - CLB, cache, spatial data locality

Autoři

TIŠNOVSKÝ, P.; HEROUT, A.; ZEMČÍK, P.

Rok RIV

2003

Vydáno

22. 9. 2003

ISSN

1213-161X

Periodikum

ElectronicsLetters.com - http://www.electronicsletters.com

Ročník

2003

Číslo

1

Stát

Česká republika

Strany počet

8

BibTex

@article{BUT42291,
  author="Pavel {Tišnovský} and Adam {Herout} and Pavel {Zemčík}",
  title="Cache-Based Parallel Particle Rendering Engine",
  journal="ElectronicsLetters.com - http://www.electronicsletters.com",
  year="2003",
  volume="2003",
  number="1",
  pages="8",
  issn="1213-161X"
}