Publication detail

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits

STRNADEL, J.

Original Title

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits

Type

journal article - other

Language

English

Original Abstract

The paper presents novel testability analysis method applicable to regis-ter-transfer level digital circuits. It is shown if each module stored in a design library is equipped both with information related to design and information related to testing, then more accurate testability results can be achieved. A mathematical model based on virtual port conception is utilized to describe the information and proposed testability analysis method. In order to be effective, the method is based on the idea of searching two special digraphs developed for the purpose. Experimental results gained by the method are presented and compared with results of existing methods.

Keywords

digital circuit, testing, register-transfer level, data-path, testability analysis, design for testability, scan technique

Authors

STRNADEL, J.

RIV year

2006

Released

7. 11. 2006

ISBN

1335-9150

Periodical

Computing and Informatics

Year of study

25

Number

5

State

Slovak Republic

Pages from

441

Pages to

464

Pages count

24

URL

https://www.fit.vut.cz/research/publication/8201/

BibTex

@article{BUT45082,
  author="Josef {Strnadel}",
  title="Testability Analysis and Improvements of Register-Transfer Level Digital Circuits",
  journal="Computing and Informatics",
  year="2006",
  volume="25",
  number="5",
  pages="441--464",
  issn="1335-9150",
  url="https://www.fit.vut.cz/research/publication/8201/"
}

Documents

2006-cai.pdf