Detail publikace

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits

STRNADEL, J.

Originální název

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits

Typ

článek v časopise - ostatní, Jost

Jazyk

angličtina

Originální abstrakt

The paper presents novel testability analysis method applicable to regis-ter-transfer level digital circuits. It is shown if each module stored in a design library is equipped both with information related to design and information related to testing, then more accurate testability results can be achieved. A mathematical model based on virtual port conception is utilized to describe the information and proposed testability analysis method. In order to be effective, the method is based on the idea of searching two special digraphs developed for the purpose. Experimental results gained by the method are presented and compared with results of existing methods.

Klíčová slova

digital circuit, testing, register-transfer level, data-path, testability analysis, design for testability, scan technique

Autoři

STRNADEL, J.

Rok RIV

2006

Vydáno

7. 11. 2006

ISSN

1335-9150

Periodikum

Computing and Informatics

Ročník

25

Číslo

5

Stát

Slovenská republika

Strany od

441

Strany do

464

Strany počet

24

URL

https://www.fit.vut.cz/research/publication/8201/

BibTex

@article{BUT45082,
  author="Josef {Strnadel}",
  title="Testability Analysis and Improvements of Register-Transfer Level Digital Circuits",
  journal="Computing and Informatics",
  year="2006",
  volume="25",
  number="5",
  pages="441--464",
  issn="1335-9150",
  url="https://www.fit.vut.cz/research/publication/8201/"
}

Dokumenty

2006-cai.pdf