Detail publikace

Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability

PEČENKA, T. SEKANINA, L. KOTÁSEK, Z.

Originální název

Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability

Typ

článek v časopise - ostatní, Jost

Jazyk

angličtina

Originální abstrakt

This article presents a new real-world application of evolutionary computing in the area of digital-circuits testing. A method is described which enables to evolve large synthetic RTL benchmark circuits with a predefined structure and testability. Using the proposed method, a new collection of synthetic benchmark circuits was developed. These benchmark circuits will be useful in a validation process of novel algorithms and tools in the area of digital-circuits testing. Evolved benchmark circuits currently represent the most complex benchmark circuits with a known level of testability. Furthermore, these circuits are the largest that have ever been designed by means of evolutionary algorithms. This work also investigates suitable parameters of the evolutionary algorithm for this problem and explores the limits in the complexity of evolved circuits.

Klíčová slova

evolutionary algorithm, digital circuit, testability analysis

Autoři

PEČENKA, T.; SEKANINA, L.; KOTÁSEK, Z.

Rok RIV

2008

Vydáno

23. 7. 2008

ISSN

1084-4309

Periodikum

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS

Ročník

13

Číslo

3

Stát

Spojené státy americké

Strany od

1

Strany do

21

Strany počet

21

URL

https://www.fit.vut.cz/research/publication/8653/

BibTex

@article{BUT48172,
  author="Tomáš {Pečenka} and Lukáš {Sekanina} and Zdeněk {Kotásek}",
  title="Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability",
  journal="ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS",
  year="2008",
  volume="13",
  number="3",
  pages="1--21",
  issn="1084-4309",
  url="https://www.fit.vut.cz/research/publication/8653/"
}

Dokumenty

todaes08.pdf