Publication detail

High-level Modeling, Analysis and Verification of Programmable Hardware Design

SMRČKA, A.

Original Title

High-level Modeling, Analysis and Verification of Programmable Hardware Design

Type

abstract

Language

English

Original Abstract

This work presents an abstract model of the design and verification of several safety properties. The main task was to check if there is a risk of buffer overflow and how to set the length of buffers to prevent this. This work shows how to model such a complex system by hand and particular results of analysis and verification is also presented.

Keywords

formal verification, high-level verification, hardware design analysis, throughput checking, timed analysis

Authors

SMRČKA, A.

Released

24. 4. 2006

Publisher

Technical University Wien

Location

Vienna

ISBN

3-902463-05-8

Book

Proceedings of the Junior Scientist Conference 2006

Pages from

93

Pages to

94

Pages count

3

BibTex

@misc{BUT60508,
  author="Aleš {Smrčka}",
  title="High-level Modeling, Analysis and Verification of Programmable Hardware Design",
  booktitle="Proceedings of the Junior Scientist Conference 2006",
  year="2006",
  pages="93--94",
  publisher="Technical University Wien",
  address="Vienna",
  isbn="3-902463-05-8",
  note="abstract"
}