Detail publikace

High-level Modeling, Analysis and Verification of Programmable Hardware Design

SMRČKA, A.

Originální název

High-level Modeling, Analysis and Verification of Programmable Hardware Design

Typ

abstrakt

Jazyk

angličtina

Originální abstrakt

This work presents an abstract model of the design and verification of several safety properties. The main task was to check if there is a risk of buffer overflow and how to set the length of buffers to prevent this. This work shows how to model such a complex system by hand and particular results of analysis and verification is also presented.

Klíčová slova

formal verification, high-level verification, hardware design analysis, throughput checking, timed analysis

Autoři

SMRČKA, A.

Vydáno

24. 4. 2006

Nakladatel

TU Vienna

Místo

Vienna

ISBN

3-902463-05-8

Kniha

Proceedings of the Junior Scientist Conference 2006

Strany od

93

Strany do

94

Strany počet

3

BibTex

@misc{BUT60508,
  author="Aleš {Smrčka}",
  title="High-level Modeling, Analysis and Verification of Programmable Hardware Design",
  booktitle="Proceedings of the Junior Scientist Conference 2006",
  year="2006",
  pages="93--94",
  publisher="TU Vienna",
  address="Vienna",
  isbn="3-902463-05-8",
  note="abstract"
}