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ŠTRAUS, P. KOLKA, Z.
Original Title
Simulation and Implementation of LDPC Code in FPGA
Type
conference paper
Language
English
Original Abstract
The paper deals with implementation of Low-Density Parity-Check (LDPC) codes [1] in FPGA-based bridge for Free-Space Optical link.The coder was designed with a regular parity matrix for code rate 1/2. The matrix of dimension 8x16 for the experimental implementation was found using a random search in MATLAB. The main advantage of this matrix is the decoder can correct all single-bit errors. The simulation for all possible values shows that Bit Error Ratio (BER) is zero. This result was not obtained with other matrices. An experimental communication channel was realized with encoder and decoder implemented in FPGA Virtex 5 development board ML505. DIP switches are sources for information bits and these values are shown on LCD display. The bit-flipping method is used in decoder and result code word is shown in the second line on the LCD display.
Keywords
LDPC, Encoder, Decoder, Bit-Flipping
Authors
ŠTRAUS, P.; KOLKA, Z.
RIV year
2013
Released
16. 4. 2013
Location
Pardubice
ISBN
978-1-4673-5517-9
Book
Microwave and Radio Electronics Week 2013
Pages from
346
Pages to
349
Pages count
4
BibTex
@inproceedings{BUT99276, author="Pavel {Štraus} and Zdeněk {Kolka}", title="Simulation and Implementation of LDPC Code in FPGA", booktitle="Microwave and Radio Electronics Week 2013", year="2013", pages="346--349", address="Pardubice", isbn="978-1-4673-5517-9" }