Detail publikace

Simulation and Implementation of LDPC Code in FPGA

ŠTRAUS, P. KOLKA, Z.

Originální název

Simulation and Implementation of LDPC Code in FPGA

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

The paper deals with implementation of Low-Density Parity-Check (LDPC) codes [1] in FPGA-based bridge for Free-Space Optical link.The coder was designed with a regular parity matrix for code rate 1/2. The matrix of dimension 8x16 for the experimental implementation was found using a random search in MATLAB. The main advantage of this matrix is the decoder can correct all single-bit errors. The simulation for all possible values shows that Bit Error Ratio (BER) is zero. This result was not obtained with other matrices. An experimental communication channel was realized with encoder and decoder implemented in FPGA Virtex 5 development board ML505. DIP switches are sources for information bits and these values are shown on LCD display. The bit-flipping method is used in decoder and result code word is shown in the second line on the LCD display.

Klíčová slova

LDPC, Encoder, Decoder, Bit-Flipping

Autoři

ŠTRAUS, P.; KOLKA, Z.

Rok RIV

2013

Vydáno

16. 4. 2013

Místo

Pardubice

ISBN

978-1-4673-5517-9

Kniha

Microwave and Radio Electronics Week 2013

Strany od

346

Strany do

349

Strany počet

4

BibTex

@inproceedings{BUT99276,
  author="Pavel {Štraus} and Zdeněk {Kolka}",
  title="Simulation and Implementation of LDPC Code in FPGA",
  booktitle="Microwave and Radio Electronics Week 2013",
  year="2013",
  pages="346--349",
  address="Pardubice",
  isbn="978-1-4673-5517-9"
}