Publication detail

Approximate Circuit Design by Means of Evolvable Hardware

SEKANINA, L. VAŠÍČEK, Z.

Original Title

Approximate Circuit Design by Means of Evolvable Hardware

Type

conference paper

Language

English

Original Abstract

This paper deals with evolutionary design of approximate circuits. This class of circuits is characterized by relaxing the requirement on functional equivalence between the specification and implementation in order to reduce the area on a chip or minimize energy consumption. We proposed a CGP-based automated design method which enables to find a good trade off between key circuit parameters (functionality, area and power consumption). In particular, the digital approximate circuits consisting of elementary gates are addressed in this paper. Experimental results are provided for combinational single-output circuits and adders where two different metrics are compared for the error assessment.

Keywords

approximate circuit, evolutionary design, multiplier, adder

Authors

SEKANINA, L.; VAŠÍČEK, Z.

RIV year

2013

Released

16. 4. 2013

Publisher

IEEE Computer Society

Location

Singapur

ISBN

978-1-4673-5847-7

Book

2013 IEEE International Conference on Evolvable Systems (ICES)

Edition

Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI)

Pages from

21

Pages to

28

Pages count

8

URL

https://www.fit.vut.cz/research/publication/10198/

BibTex

@inproceedings{BUT103438,
  author="Lukáš {Sekanina} and Zdeněk {Vašíček}",
  title="Approximate Circuit Design by Means of Evolvable Hardware",
  booktitle="2013 IEEE International Conference on Evolvable Systems (ICES)",
  year="2013",
  series="Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI)",
  pages="21--28",
  publisher="IEEE Computer Society",
  address="Singapur",
  doi="10.1109/ICES.2013.6613278",
  isbn="978-1-4673-5847-7",
  url="https://www.fit.vut.cz/research/publication/10198/"
}

Documents

sekanina_vasicek.pdf