Publication detail

Hardware Accelerators for Cartesian Genetic Programming

VAŠÍČEK, Z. SEKANINA, L.

Original Title

Hardware Accelerators for Cartesian Genetic Programming

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP).  The accelerators contain a genetic engine which is reused in all applications. Candidate programs (circuits) are evaluated using application-specific virtual reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed. The first one is devoted for symbolic regression problems over the fixed point representation. The second one is designed for evolution of logic circuits. In both cases a significant speedup of evolution (30-40 times) was obtained in comparison with a highly optimized software implementation of CGP. This speedup can be increased by creating multiple fitness units.

Keywords

cartesian genetic programming, field programmable gate array, evolutionary design

Authors

VAŠÍČEK, Z.; SEKANINA, L.

RIV year

2008

Released

30. 3. 2008

Publisher

Springer Verlag

Location

Berlin

ISBN

978-3-540-78670-2

Book

Eleventh European Conference on Genetic Programming

Edition

Lecture Notes in Computer Science

Pages from

230

Pages to

241

Pages count

12

URL

https://www.fit.vut.cz/research/publication/8590/

BibTex

@inproceedings{BUT30754,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Hardware Accelerators for Cartesian Genetic Programming",
  booktitle="Eleventh European Conference on Genetic Programming",
  year="2008",
  series="Lecture Notes in Computer Science",
  volume="4971",
  pages="230--241",
  publisher="Springer Verlag",
  address="Berlin",
  isbn="978-3-540-78670-2",
  url="https://www.fit.vut.cz/research/publication/8590/"
}

Documents

49710230.pdf