Publication detail

Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration

KAŠTIL, J. STRAKA, M. KOTÁSEK, Z.

Original Title

Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In the paper, the activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. The methodology supports the detection a localization of all soft errors in the design and recovery mechanism which is based on the principles of partial dynamic reconfiguration of the chip. The main features of methodology are presented in the paper.

Keywords

FPGA, partial dynamic reconfiguration, reliability, redundancy, checker, SEU, controller

Authors

KAŠTIL, J.; STRAKA, M.; KOTÁSEK, Z.

Released

28. 2. 2012

Publisher

Politecnico di Milano

Location

Annecy

Pages from

1

Pages to

4

Pages count

4

BibTex

@inproceedings{BUT91473,
  author="Jan {Kaštil} and Martin {Straka} and Zdeněk {Kotásek}",
  title="Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration",
  booktitle="The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)",
  year="2012",
  pages="1--4",
  publisher="Politecnico di Milano",
  address="Annecy"
}