Course detail

VHDL Seminar

FIT-IVHAcad. year: 2017/2018

Basic VHDL language constructs, lexical description, VHDL source code. Data types, data objects, data classes, data objects declaration. VHDL language commands. Advanced VHDL features, VHDL 93. Delay modelling, time scheduling in VHDL. Combinational circuits modelling, "don't cares", tri-state-output circuits. Sequential circuits modelling, Mealy and Moore automata. Models testing, test benches. Designing at algorithm, register-transfer, and gate levels. Modelling for synthesis. Semantics for simulation and synthesis, delay in model. Programming techniques, shared components, flattening and structuring. Case studies of complex digital circuits: UART, RISC processor, FIR filter.

Language of instruction

Czech

Number of ECTS credits

4

Mode of study

Not applicable.

Guarantor

doc. Ing. Zdeněk Vašíček, Ph.D.

Department

Department of Computer Systems (UPSY)

Learning outcomes of the course unit

The student should be able to describe and simulate complex digital systems using VHLD language constructs including both behavioral and structural description.

Prerequisites

Basic skills in programming and digital design, fundamentals of Boolean algebra.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

Class credit is based on the quality of the class project. The minimal number of points which are required from the project is 50. Otherwise, no credit will be assigned to a student.

Course curriculum

    Syllabus of lectures:
    1. Moderní návrh hardware (design flow), jazyky pro popis hardware (VHDL, Verilog), FPGA, úvod do číslicových systémů.
    2. Základní konstrukce jazyka VHDL, lexikální popis, zdrojový text ve VHDL.
    3. Datové typy, datové objekty, třídy objektů, deklarace datových objektů.
    4. Příkazy jazyka VHDL
    5. Pokročilé vlastnosti jazyka VHDL, zpoždění a plánování času.
    6. Popis kombinačních obvodů, třístavové obvody.
    7. Popis synchronních sekvenčních obvodů, popis konečných automatů, asynchronní sekvenční obvody.
    8. Modelování obvodů a událostně řízená simulace, testování obvodů a návrh testů, funkční simulace (ModelSIM), co-simulace.
    9. Syntéza obvodů, omezení (constraints), syntéza pro FPGA, časová simulace.
    10. Pokročilé techniky (pipelining, retiming, sdílení komponent, flattening a strukturování)
    11. Příkladová studie komplexních obvodů: řízení maticového LED displeje, UART, ETHERNET
    12. Příkladová studie komplexních obvodů: RISC procesor
    13. Obvody FPGA, využití masivního paralelismu v kryptografii (RC4, DES), DNA-alignment

    Syllabus - others, projects and individual work of students:
    Individual project.

Work placements

Not applicable.

Aims

To give the students the knowledge of syntax and semantics of hardware description language VHDL, its use for modelling, simulation, and synthesis of complex digital systems, as well as the skills in VHDL programming techniques and the use of professional design tools.

Specification of controlled education, way of implementation and compensation for absences

Project and its defence supported by the written technical report in English language.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Not applicable.

Recommended reading

Přednáškové materiály v elektronické podobě. (CS)

Classification of course in study plans

  • Programme IT-BC-3 Bachelor's

    branch BIT , 1 year of study, summer semester, compulsory-optional
    branch BIT , 2 year of study, summer semester, compulsory-optional

Type of course unit

 

Fundamentals seminar

26 hod., optionally

Teacher / Lecturer

doc. Ing. Zdeněk Vašíček, Ph.D.

Project

13 hod., optionally

Teacher / Lecturer

doc. Ing. Zdeněk Vašíček, Ph.D.