Course detail

Programmable Logic Devices

FEKT-MPLDAcad. year: 2018/2019

Students get more detailed knowledge in the area of digital circuits design, especially with respect to their implementation into PLDs (FPGAs, CPLDs) and ASICs. Students get overview of current technology of these integrated circuits, their off-the-shelf architectures, principles of design and application of basic digital subsystems (counters, finite state machines, memory structures). During the PC lectures students get familiar with modern system for FPGA configuration. This includes description of the digital system (using VHDL source codes, schematic, IP cores), its implementation and verification using simulator. After passing the course students are able to design and implement simple digital system into an FPGA (using VHDL language).

Language of instruction

Czech

Number of ECTS credits

6

Mode of study

Not applicable.

Guarantor

Ing. Michal Kubíček, Ph.D.

Department

Department of Radio Electronics (UREL)

Learning outcomes of the course unit

The graduate is able to
- describe simple digital system using VHDL
- verify simple digital system using VHDL
- choose type of finite state machine and give reasons for the choice
- design and implement a finite state machine using VHDL
- compare different architectures of PLDs and choose a proper one for particular application
- specify timing requirements for a design and verify that they are met after implementation
- implement simple IP cores like memories and simple DSP blocks (FIR filtres)
- implement simple microcontroller into FPGA, program it and use in target application
- state requirements on FPGA power supply system
- analyze and prevent/solve basic signal integrity issue

Prerequisites

Students are expected to know basic of impulse and digital technology: the Boolean algebra, Karnaugh maps, truth tables, function of basic gates and flip-flops (registers), principle and effect of signal propagation through active and passive transmission elements.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Techning methods include lectures and computer laboratories. Course is taking advantage of e-learning (Moodle) system. The main focus is on computer laboratories with strong emphasis on practical skills.

Assesment methods and criteria linked to learning outcomes

Students obtain points for the activity in computer labs during the semester. The final exam is composed of written, practical and oral part.

Course curriculum

1. Introduction to digital integrated circuits, history and development of CPLDs and FPGAs
2. Introduction to VHDL programming language
3. The basics of digital systems: gates, flip-flops, shift registers, counters
4. Moor and Mealy state machines
5. Practical design and application of finite state machines, microsequencers
6. Basis architecture of FPGAs and CPLDs: logic cells, programmable interconnect, I/O cells
7. Timing of digital circuits, metastability, methods for increasing clock frequency
8. FPGA clock domains, clock enabling, clock management, synchronous and asynchronous reset
9. Memory structures in FPGAs, use of RAM, ROM and FIFO
10. Digital signal processing in FPGAs, dedicated blocks for DSP acceleration
11. Advanced FPGA structural features, HARD and SOFT IP cores, implementation of basic IP cores
12. Processors in FPGA, SoC, FPGA manufacturing technology, FPGA configuration
13. Signal integrity, PCB and power design for FPGA, radiation effects.

Work placements

Not applicable.

Aims

Lectures are aimed to teach students the basic principles of modern PLDs, particularly CPLDs and FPGAs, while they will be able not only to configure (program) them, but also select proper device and implement it into a system.

Specification of controlled education, way of implementation and compensation for absences

Evaluation of activities is specified by a regulation, which is issued by the lecturer responsible for the course annually.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

KOLOUCH, J.: Programovatelné logické obvody - přednášky. [Skriptum FEKT VUT v Brně.] MJ servis, Brno 2005 (CS)
KOLOUCH, J.: Programovatelné logické obvody a návrh jejich aplikací v jazyku VHDL - počítačové cvičení. [Skriptum FEKT VUT v Brně.] MJ servis, Brno 2005 (CS)

Recommended reading

WAKERLY, J.: Digital Design - principles and practices. 4-th Ed. Pearson Education LTD, Prentice Hall, 2005 (EN)

Classification of course in study plans

  • Programme EEKR-M Master's

    branch M-MEL , 1 year of study, summer semester, elective interdisciplinary
    branch M-EST , 1 year of study, summer semester, elective specialised
    branch M-SVE , 1 year of study, summer semester, elective interdisciplinary
    branch M-TIT , 1 year of study, summer semester, elective interdisciplinary

  • Programme IBEP-V Master's

    branch V-IBP , 1 year of study, summer semester, elective specialised
    branch V-IBP , 2 year of study, summer semester, elective specialised

  • Programme EEKR-CZV lifelong learning

    branch EE-FLE , 1 year of study, summer semester, elective specialised

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

Ing. Michal Kubíček, Ph.D.

Syllabus

Survey of ways how to implement digital systems. Logic functions, their realization in PROM, PAL, PLA structures . ASSP and ASIC devices.
Simple PLDs, their functional blocks, macrocells of GAL 16V8 and 20V8 devices. Other SPLD types, their labelling and parameters
Complex PLD and FPGA devices - structure, basic properties
Introduction to VHDL programming language, synthesis and implementation (translation, mapping, place and route), constraints
Asynchronous (combinational) and synchronous (sequence) logic systems in PLDs.
Counters: binary, decimal (one- and bidirectional, with shortened cycle), Gray counter, LFSR – properties, HDL description
State machines (SM): Moore and Mealy type, HDL description, their compilation to SOP form
Simplifying of SM - equivalent states, their finding. State coding for PLDs and FPGAs. Algorithmic description of SM
Timing in programmable devices, pipelining, register retiming. Metastability, usage of reset signal and corresponding HDL description
FPGA devices - additional blocks: I/O standards, memory elements, blocks for frequency synthesis and for further handling of clock signals, fast serial communication, DSP blocks
Implementation of processors, use of intellectual property blocks
Boundary scan, PLD configuration, PCB design for PLD.

Exercise in computer lab

39 hod., compulsory

Teacher / Lecturer

Ing. Jan Král, Ph.D.
Ing. Michal Harvánek, Ph.D.

Syllabus

Introduction to VHDL and ISE design tool
Basic functions, combinational logic (decoding)
Hierarchical design, usage of schematic
Implementation of sequential systems (counters)
State machines and their VHDL description
Structural description, testbench, simulation
LFSR counter, timing parameters, power consumption of FPGA
Usage of IP cores
Usage of ChipScope tool
Microprocessors in FPGA - PicoBlaze, MicroBlaze