Course detail

Design of Computer Systems

FIT-INPAcad. year: 2025/2026

Processor operating principle. Von Neumann computer. Data types, formats, and coding. Instructions, formats, coding and addressing, instruction set architecture. VHDL models of algorithms and subsystems. Instruction pipelining. Arithmetic and logic operations in fixed and floating-point number representation. Controllers: basic function, hard-wired and microprogram implementation. Memories: types, organization, control. Memory hierarchy, cache memory. Peripheral units, buses and bus control. Performance evaluation. Reliability of computer systems. Introduction to parallel architectures.

Language of instruction

Czech

Number of ECTS credits

6

Mode of study

Not applicable.

Guarantor

prof. Ing. Lukáš Sekanina, Ph.D.

Department

Department of Computer Systems (UPSY)

Entry knowledge

Not applicable.

Rules for evaluation and completion of the course

Exam prerequisites: For receiving the credit and thus for entering the exam, students have to get at least 20 points during the semester. Plagiarism and not allowed cooperation will cause that involved students are not classified and disciplinary action can be initiated.
Within this course, attendance on the lectures and demonstrations is not monitored. The knowledge of students is examined by the projects, the mid-term exam and by the final exam. The minimal number of points which can be obtained from the final exam is 20. Otherwise, no points will be assigned to a student. In the case of a reported barrier preventing the student to perform the scheduled activity, the guarantor can allow the student to perform this activity on an alternative date.

Aims

To give the students knowledge of organization and functioning of a (single core) processor, in particular, the principles of the operation, memory and control units, the algorithms with fixed and floating point number systems, the subsystem communication level, and integration of the processor to a parallel system.

After completing this course, students will be able to describe the functionality of the computation, memory and control units, and their communication in a digital computer. They will be familiar with the basics of VHDL. They will understand the development trends and limitations of computer technology.

Study aids

Not applicable.

Prerequisites and corequisites

Basic literature

Drábek V.: Výstavba počítačů, skripta VUT v Brně, PC-DIR, Brno, 1995. (CS)
Hamacher, C., Vranesic, Z., Zaky, S., N. Manjikian: Computer Organization and Embedded Systems, 6th edition, McGraw Hill, 2012, ISBN-13: 978-0-07-338065-0
Hennessy J. L., Patterson D. A.: Computer Architecture: A Quantitative Approach, 2nd edition, Morgan Kaufmann Publ., 1996, and new editions, e.g. the 5th ed. from 2012.

Recommended reading

Pinker J., Poupa M.: Číslicové systémy a jazyk VHDL, BEN - technická literatura, Praha, 2006. (CS)

Classification of course in study plans

  • Programme BIT Bachelor's 2 year of study, winter semester, compulsory
  • Programme BIT Bachelor's 2 year of study, winter semester, compulsory

Type of course unit

 

Lecture

39 hod., optionally

Teacher / Lecturer

prof. Ing. Lukáš Sekanina, Ph.D.
doc. Ing. Michal Bidlo, Ph.D.

Syllabus

  1. Introduction, processor and its organization.
  2. Instruction sets, register structures.
  3. Pipelining in processors.
  4. Data representation.
  5. Algorithms of fixed-point operations.
  6. Algorithms of floating point operations, iterative algorithms.
  7. Controllers.
  8. Memory.
  9. Cache memory.
  10. Buses, peripheral interfacing and control.
  11. Computer performance and performance evaluation.
  12. Reliability of computer systems.
  13. Introduction to parallel architectures.

Seminar

12 hod., optionally

Teacher / Lecturer

doc. Ing. Zdeněk Vašíček, Ph.D.
Ing. Vojtěch Mrázek, Ph.D.

Syllabus

  1. VHDL - introduction
  2. VHDL - synthesizable code
  3. FPGA
  4. Processor in VHDL
  5. Huffman code, Hamming code
  6. Modular arithmetic, adders
  7. Multipliers
  8. Division
  9. Iterative algorithms
  10. Performance evaluation, reliability
  11. Parallel Architectures

Project

14 hod., compulsory

Teacher / Lecturer

doc. Ing. Zdeněk Vašíček, Ph.D.
doc. Ing. Michal Bidlo, Ph.D.

Syllabus

  • Two projects will be assigned during the semester.