Publikace

• 2021

  LOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; KOTÁSEK, Z. Accelerating Tests of Arithmetic Circuits Through On-FPGA Stimuli Generation and Their Reduction. In International Conference on Electrical, Computer, Communications and Mechatronics Engineering, ICECCME 2021. Mauritius: Institute of Electrical and Electronics Engineers, 2021. s. 1628-1633. ISBN: 978-1-6654-1262-9.
  Detail | WWW

  LOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. In 2021 IEEE 22nd Latin American Test Symposium, LATS 2021. Punta del Este: Institute of Electrical and Electronics Engineers, 2021. s. 80-85. ISBN: 978-1-6654-2057-0.
  Detail | WWW

• 2020

  LOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. In 2020 IEEE East-West Design and Test Symposium, EWDTS 2020 - Proceedings. Varna: Institute of Electrical and Electronics Engineers, 2020. s. 24-28. ISBN: 978-1-7281-9899-6.
  Detail | WWW

  LOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. In Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Kranj: Institute of Electrical and Electronics Engineers, 2020. s. 680-683. ISBN: 978-1-7281-9535-3.
  Detail | WWW

  LOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. In Proceedings - 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020. Novi Sad: Institute of Electrical and Electronics Engineers, 2020. s. 1-4. ISBN: 978-1-7281-9938-2.
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  PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z. Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination. In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). San José: IEEE Circuits and Systems Society, 2020. s. 1-4. ISBN: 978-1-7281-3427-7.
  Detail | WWW

  PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). San José: IEEE Circuits and Systems Society, 2020. s. 1-4. ISBN: 978-1-7281-3427-7.
  Detail | WWW

• 2019

  ČEKAN, O.; PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Smart Electronic Locks and Their Reliability. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2019. s. 4-5. ISBN: 978-80-01-06607-2.
  Detail | WWW

  PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z. Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2019. s. 20-21. ISBN: 978-80-01-06607-2.
  Detail | WWW

  ČEKAN, O.; PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. In Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019. s. 506-513. ISBN: 978-1-7281-2861-0.
  Detail | WWW

  PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z. Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. In Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019. s. 597-600. ISBN: 978-1-7281-2861-0.
  Detail | WWW

• 2018

  ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Program Generation Through a Probabilistic Constrained Grammar. In Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. Praha: IEEE Computer Society, 2018. s. 214-220. ISBN: 978-1-5386-7376-8.
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  ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. Input and Output Generation for the Verification of ALU: a Use Case. In Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018. Kazan: IEEE Computer Society, 2018. s. 331-336. ISBN: 978-1-5386-5710-2.
  Detail | WWW

  ČEKAN, O.; KOTÁSEK, Z. Random Test Generation Through a Probabilistic Constrained Grammar. INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť: 2018. s. 5-8.
  Detail

  LOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation. In Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018. s. 244-251. ISBN: 978-1-5386-7376-8.
  Detail | WWW

  PODIVÍNSKÝ, J.; LOJDA, J.; ČEKAN, O.; KOTÁSEK, Z. Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018. s. 229-236. ISBN: 978-1-5386-7376-8.
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  PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z. A Framework for Optimizing a Processor to Selected Application. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018. s. 564-574. ISBN: 978-1-5386-5710-2.
  Detail | WWW

• 2017

  ČEKAN, O.; KOTÁSEK, Z. Random Test Stimuli Generation Based on a Probabilistic Grammar. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017. s. 43-44. ISBN: 978-80-01-06178-7.
  Detail | WWW

  ČEKAN, O.; KOTÁSEK, Z. A Probabilistic Context-Free Grammar Based Random Test Program Generation. In Proceedings of 20th Euromicro Conference on Digital System Design. Vídeň: Technical University Wien, 2017. s. 356-359. ISBN: 978-1-5386-2145-5.
  Detail | WWW

  PODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; ZACHARIÁŠOVÁ, M.; KRČMA, M.; KOTÁSEK, Z. Functional Verification Based Platform for Evaluating Fault Tolerance Properties. Microprocessors and Microsystems, 2017, roč. 52, č. 5, s. 145-159. ISSN: 0141-9331.
  Detail | WWW

  PODIVÍNSKÝ, J.; LOJDA, J.; ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. Reliability Analysis and Improvement of FPGA-based Robot Controller. In Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Vídeň: IEEE Computer Society, 2017. s. 337-344. ISBN: 978-1-5386-2145-5.
  Detail | WWW

• 2016

  PODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; KOTÁSEK, Z. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. In Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016. s. 487-494. ISBN: 978-1-5090-2816-0.
  Detail | WWW

  ČEKAN, O. Generování testovacích stimulů. Počítačové architektury a diagnostika PAD 2016. Bořetice - Kraví Hora: Fakulta informačních technologií VUT v Brně, 2016. s. 97-100. ISBN: 978-80-214-5376-0.
  Detail | WWW

  ČEKAN, O.; KOTÁSEK, Z. Software-implemented Fault-Tolerant Program Generation. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016. s. 13-13. ISBN: 978-80-01-05984-5.
  Detail

  ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Random Stimuli Generation Based on a Stochastic Context-Free Grammar. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. s. 295-296. ISBN: 978-1-5090-5602-6.
  Detail

  PODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; KOTÁSEK, Z. Functional Verification as a Tool for Monitoring Impact of Faults in SRAM-based FPGAs. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. s. 293-294. ISBN: 978-1-5090-5602-6.
  Detail | WWW

• 2015

  PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. Microprocessors and Microsystems, 2015, roč. 39, č. 8, s. 1215-1230. ISSN: 0141-9331.
  Detail | WWW

  PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; ČEKAN, O.; KOTÁSEK, Z. FPGA Prototyping and Accelerated Verification of ASIPs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. s. 145-148. ISBN: 978-1-4799-6780-3.
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  ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Software Fault Tolerance: the Evaluation by Functional Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. s. 284-287. ISBN: 978-1-4673-8035-5.
  Detail | WWW

  ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Universal Pseudo-random Generation of Assembler Codes for Processors. Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015. s. 70-73.
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  ČEKAN, O. Principy generování verifikačních stimulů. Počítačové architektury a diagnostika PAD 2015. Zlín: Fakulta aplikované informatiky, Univerzita Tomáše Bati ve Zlíně, 2015. s. 13-18. ISBN: 978-80-7454-522-1.
  Detail | WWW

• 2014

  PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. s. 312-319. ISBN: 978-1-4799-5793-4.
  Detail | WWW

  ČEKAN, O. Universal Generation of Test Vectors for Functional Verification. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. s. 44-49. ISBN: 978-80-7494-027-9.
  Detail

  ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Solving of Constraint Satisfaction Problem. Proceedings of the 20th Conference STUDENT EEICT 2014. Volume 3. Brno: Faculty of Information Technology BUT, 2014. s. 291-295. ISBN: 978-80-214-4924-4.
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*) Citace publikací se generují jednou za 24 hodin.