Detail projektu

Pokročilé metody evolučního návrhu složitých číslicových obvodů

Období řešení: 01.01.2014 — 31.12.2016

Zdroje financování

Grantová agentura České republiky - Standardní projekty

- plně financující (2014-01-01 - 2016-12-31)

O projektu

Evoluční návrh obvodů je metoda, která používá biologií inspirované prohledávací algoritmy pro syntézu a optimalizaci elektronických obvodů. Ačkoliv evoluční návrh umožnil získat mnoho zajímavých výsledků, nemožnost dobré škálovatelnosti zůstává hlavní nevýhodou metody. V tomto projektu navrhujeme a obhajujeme nové přístupy k evolučnímu návrhu obvodů, které umožní eliminovat problém škálovatelnosti a dovolí vytvářet a optimalizovat složité číslicové obvody a adaptivní hardware v programovatelných hradlových polích (FPGA). Navrhovaný projekt předpokládá následující výsledky: (1) Nové algoritmy pro ověřování funkční ekvivalence, které umožní urychlit výpočet fitness. (2) Nové vícekriteriální a koevoluční algoritmy pro evoluční návrh. (3) Rutinní návrh a optimalizace složitých číslicových obvodů pomocí navržených metod. (4) Nové architektury pro vyvíjející se a adaptivní systémy implementované v FPGA.

Popis anglicky
The evolutionary circuit design is the use of bio-inspired search algorithms for automated synthesis and optimization of electronic circuits. Although many interesting results have been obtained using the evolutionary design, the scalability problem is still considered as the most significant problem of the method. In this project, we propose and advocate new approaches to evolutionary circuit design that will enable us to eliminate the scalability problem and thus construct and optimize complex digital circuits and adaptive hardware systems in field programmable gate arrays (FPGA). The following results are projected: (1) New functional equivalence checking algorithms for accelerating the fitness calculation. (2) New multiobjective and co-evolutionary design algorithms. (3) Routine design and optimization of complex circuits by means of the proposed tools. (4) New architectures of FPGA-based evolvable hardware systems. 

Klíčová slova
Evoluční návrh obvodů, evoluční hardware, programovatelná hradlová pole, koevoluce

Klíčová slova anglicky
Evolutionary circuit design, evolvable hardware, field programmable gate array, co-evolution

Označení

GA14-04197S

Originální jazyk

čeština

Řešitelé

Sekanina Lukáš, prof. Ing., Ph.D. - hlavní řešitel
Bidlo Michal, doc. Ing., Ph.D. - spoluřešitel
Dobai Roland, Ing., Ph.D. - spoluřešitel
Drahošová Michaela, Ing., Ph.D. - spoluřešitel
Dvořák Milan, Ing. - spoluřešitel
Grochol David, Ing., Ph.D. - spoluřešitel
Hrbáček Radek, Ing., Ph.D. - spoluřešitel
Minařík Miloš, Ing., Ph.D. - spoluřešitel
Mrázek Vojtěch, Ing., Ph.D. - spoluřešitel
Petrlík Jiří, Ing., Ph.D. - spoluřešitel
Vašíček Zdeněk, doc. Ing., Ph.D. - spoluřešitel

Útvary

Ústav počítačových systémů
- příjemce (03.04.2013 - 31.12.2016)

Výsledky

DOBAI, R.; GLETTE, K.; TORRESEN, J.; SEKANINA, L. Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in Field Programmable Gate Arrays. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 85-92. ISBN: 978-1-4799-4480-4.
Detail

SEKANINA, L.; VAŠÍČEK, Z. Genetic Improvement for Approximate Computing. 2nd Workshop on Approximate Computing (WAPCO 2016). Prague: 2016. p. 1-2.
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MINAŘÍK, M.; SEKANINA, L. Exploring the Search Space of Hardware / Software Embedded Systems by Means of GP. In Genetic Programming, 17th European Conference, EuroGP 2014. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2014. p. 112-123. ISBN: 978-3-662-44302-6.
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BIDLO, M.; VAŠÍČEK, Z. On Evolution of Multi-Category Pattern Classifiers Suitable for Embedded Systems. In Genetic Programming, 17th European Conference, EuroGP 2014. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2014. p. 234-245. ISBN: 978-3-662-44302-6.
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SEKANINA, L.; PTÁK, O.; VAŠÍČEK, Z. Cartesian Genetic Programming as Local Optimizer of Logic Networks. In 2014 IEEE Congress on Evolutionary Computation. Beijing: IEEE Computational Intelligence Society, 2014. p. 2901-2908. ISBN: 978-1-4799-1488-3.
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HRBÁČEK, R.; SEKANINA, L. Towards Highly Optimized Cartesian Genetic Programming: From Sequential via SIMD and Thread to Massive Parallel Implementation. In GECCO '14 Proceedings of the 2014 conference on Genetic and evolutionary computation. New York: Association for Computing Machinery, 2014. p. 1015-1022. ISBN: 978-1-4503-2662-9.
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VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Design of Approximate Multipliers Under Different Error Metrics. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warsaw: IEEE Computer Society, 2014. p. 135-140. ISBN: 978-1-4799-4558-0.
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BIDLO, M. Evolution of Computational Structures in Uniform Cellular Automata. In 2014 IEEE Congress on Evolutionary Computation (CEC). Beijing: IEEE Computational Intelligence Society, 2014. p. 2732-2739. ISBN: 978-1-4799-1488-3.
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DOBAI, R. Evolutionary On-line Synthesis of Hardware Accelerators for Software Modules in Reconfigurable Embedded Systems. In 2014 24th International Conference on Field Programmable Logic and Applications (FPL). Munich: Institute of Electrical and Electronics Engineers, 2014. p. 1-6. ISBN: 978-3-00-044645-0.
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HRBÁČEK, R.; DVOŘÁK, V. Bent Function Synthesis by Means of Cartesian Genetic Programming. In Parallel Problem Solving from Nature - PPSN XIII. Heidelberg: Springer Verlag, 2014. p. 414-423. ISBN: 978-3-319-10761-5.
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SEKANINA, L.; VAŠÍČEK, Z. On Evolutionary Approximation of Logic Circuits. In Computing with New Resources. Berlin: Springer Verlag, 2014. p. 367-378. ISBN: 978-3-319-13349-2.
Detail

DRAHOŠOVÁ, M.; KOMJÁTHY, G.; SEKANINA, L. Towards Compositional Coevolution in Evolutionary Circuit Design. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 157-164. ISBN: 978-1-4799-4479-8.
Detail

VAŠÍČEK, Z.; SEKANINA, L. How to Evolve Complex Combinational Circuits From Scratch?. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 133-140. ISBN: 978-1-4799-4480-4.
Detail

HRBÁČEK, R. Bent Functions Synthesis on Xeon Phi Coprocessor. In Mathematical and Engineering Methods in Computer Science. Lecture Notes in Computer Science. Heidelberg: Springer Verlag, 2014. p. 88-99. ISBN: 978-3-319-14895-3.
Detail

MRÁZEK, V. Akcelerace evolučního návrhu digitálních obvodů na úrovni tranzistorů s využitím platformy Zynq. Proceedings of the 20th Student Conference, EEICT 2014. Volume 2. Brno: Vysoké učení technické v Brně, 2014. s. 229-231. ISBN: 978-80-214-4923-7.
Detail

MRÁZEK, V.; VAŠÍČEK, Z. Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 9-16. ISBN: 978-1-4799-4480-4.
Detail

SEKANINA, L.; VAŠÍČEK, Z. Functional Equivalence Checking for Evolution of Complex Digital Circuits. In Evolvable Hardware - From Practice to Application. Berlin: Springer Verlag, 2015. p. 175-189. ISBN: 978-3-662-44615-7.
Detail

VAŠÍČEK, Z.; SEKANINA, L. Circuit Approximation Using Single- and Multi-Objective Cartesian GP. In Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. p. 217-229. ISBN: 978-3-319-16500-4.
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VAŠÍČEK, Z. Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates. In Genetic Programming, 18th European Conference, EuroGP 2015. LCNS 9025. Berlin: Springer International Publishing, 2015. p. 139-150. ISBN: 978-3-319-16500-4.
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GROCHOL, D.; SEKANINA, L.; ŽÁDNÍK, M.; KOŘENEK, J. A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. In Applications of Evolutionary Computation, 18th European Conference. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. p. 67-78. ISBN: 978-3-319-16548-6.
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MRÁZEK, V.; VAŠÍČEK, Z. Evolutionary Design of Transistor Level Digital Circuits using Discrete Simulation. In Genetic Programming, 18th European Conference, EuroGP 2015. LCNS 9025. Berlin: Springer International Publishing, 2015. p. 66-77. ISBN: 978-3-319-16500-4.
Detail

DRAHOŠOVÁ, M.; HULVA, J.; SEKANINA, L. Indirectly Encoded Fitness Predictors Coevolved with Cartesian Programs. In Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. p. 113-125. ISBN: 978-3-319-16500-4.
Detail

HRBÁČEK, R. Parallel Multi-Objective Evolutionary Design of Approximate Circuits. In GECCO '15 Proceedings of the 2015 conference on Genetic and evolutionary computation. New York: Association for Computing Machinery, 2015. p. 687-694. ISBN: 978-1-4503-3472-3.
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BIDLO, M. On Routine Evolution of New Replicating Structures in Cellular Automata. In 7th International Conference on Evolutionary Computationa Theory and Applications. 7th International Joint Conference on Computational Intelligence. Lisbon: SciTePress - Science and Technology Publications, 2015. p. 28-38. ISBN: 978-989-758-157-1.
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MRÁZEK, V.; VAŠÍČEK, Z. Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. In Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing. Porto: Institute of Electrical and Electronics Engineers, 2015. p. 106-113. ISBN: 978-1-4673-8299-1.
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MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Approximation of Software for Embedded Systems: Median Function. In GECCO Companion '15 Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. ACM. New York: Association for Computing Machinery, 2015. p. 795-801. ISBN: 978-1-4503-3488-4.
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DOBAI, R.; KOŘENEK, J. Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications. In 2015 IEEE Symposium Series on Computational Intelligence. Cape Town: Institute of Electrical and Electronics Engineers, 2015. p. 1214-1219. ISBN: 978-1-4799-7560-0.
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BIDLO, M. Investigation of Replicating Tiles in Cellular Automata Designed by Evolution Using Conditionally Matching Rules. In 2015 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2015 IEEE Symposium Series on Computational Intelligence (SSCI). Cape Town: IEEE Computational Intelligence Society, 2015. p. 1506-1513. ISBN: 978-1-4799-7560-0.
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GROCHOL, D.; SEKANINA, L.; KOŘENEK, J.; ŽÁDNÍK, M.; KOŠAŘ, V. Evolutionary Circuit Design for Fast FPGA-Based Classification of Network Application Protocols. APPLIED SOFT COMPUTING, 2016, vol. 38, no. 1, p. 933-941. ISSN: 1568-4946.
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VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Design of Complex Approximate Combinational Circuits. Genetic Programming and Evolvable Machines, 2016, vol. 17, no. 2, p. 169-192. ISSN: 1389-2576.
Detail

SÁNCHEZ-CLEMENTE, A.; ENTRENA, L.; HRBÁČEK, R.; SEKANINA, L. Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. IEEE TRANSACTIONS ON RELIABILITY, 2016, vol. 65, no. 4, p. 1871-1883. ISSN: 0018-9529.
Detail

WIGLASZ, M.; DRAHOŠOVÁ, M. Plastic Fitness Predictors Coevolved with Cartesian Programs. In 19th European Conference on Genetic programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2016. p. 164-179. ISBN: 978-3-319-30667-4.
Detail

SEKANINA, L. Introduction to Approximate Computing: Embedded Tutorial. In 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Košice: Institute of Electrical and Electronics Engineers, 2016. p. 90-95. ISBN: 978-1-5090-2467-4.
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GROCHOL, D.; SEKANINA, L. Evolutionary Design of Fast High-quality Hash Functions for Network Applications. In GECCO '16 Proceedings of the 2016 on Genetic and Evolutionary Computation Conference. New York, NY: Association for Computing Machinery, 2016. p. 901-908. ISBN: 978-1-4503-4206-3.
Detail

VAŠÍČEK, Z.; SEKANINA, L. Search-based synthesis of approximate circuits implemented into FPGAs. In 26th International Conference on Field Programmable Logic and Applications. Lausanne: Institute of Electrical and Electronics Engineers, 2016. p. 1-4. ISBN: 978-2-8399-1844-2.
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BIDLO, M. Evolution of Generic Square Calculations in Cellular Automata. In Proceedings of the 8th International Joint Conference on Computational Intelligence - Volume 3: ECTA. Porto: SciTePress - Science and Technology Publications, 2016. p. 94-102. ISBN: 978-989-758-201-1.
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BIDLO, M. Evolution of Complex Emergent Behaviour in Multi-State Cellular Automata. In Proceedings of the 2016 on Genetic and Evolutionary Computation Conference Companion. New York: Association for Computing Machinery, 2016. p. 157-158. ISBN: 978-1-4503-4323-7.
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BIDLO, M. On Routine Evolution of Complex Cellular Automata. IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, 2016, vol. 20, no. 5, p. 742-754. ISSN: 1089-778X.
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MRÁZEK, V.; SARWAR, S.; SEKANINA, L.; VAŠÍČEK, Z.; ROY, K. Design of Power-Efficient Approximate Multipliers for Approximate Artificial Neural Networks. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Austin, TX: Association for Computing Machinery, 2016. p. 811-817. ISBN: 978-1-4503-4466-1.
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VAŠÍČEK, Z.; MRÁZEK, V. Trading between Quality and Non-functional Properties of Median Filter in Embedded Systems. Genetic Programming and Evolvable Machines, 2017, vol. 18, no. 1, p. 45-82. ISSN: 1389-2576.
Detail

SEKANINA, L.; VAŠÍČEK, Z. Evolutionary Computing in Approximate Circuit Design and Optimization. 1st Workshop on Approximate Computing (WAPCO 2015). Amsterdam: 2015. p. 1-6.
Detail

DOBAI, R.: ZyEHW; ZyEHW: Evolvable hardware in Xilinx Zynq-7000 field-programmable gate arrays. Bitbucket (https://bitbucket.org/dobairoland/zyehw), Github. URL: https://www.fit.vut.cz/research/product/381/. (software)
Detail

Odpovědnost: Sekanina Lukáš, prof. Ing., Ph.D.