Vysoké učení technické v Brně - Vnitřní projekty VUT

- plně financující (2023-01-01 - 2024-12-31)

FIT-S-23-8141

čeština

Sekanina Lukáš, prof. Ing., Ph.D. - hlavní řešitel
Bardonek Petr, Ing. - spoluřešitel
Bidlo Michal, doc. Ing., Ph.D. - spoluřešitel
Blašková Barbora, Ing. - spoluřešitel
Duchoň Radek, Ing. - spoluřešitel
Fukač Tomáš, Ing., Ph.D. - spoluřešitel
Hejcman Lukáš, Ing. - spoluřešitel
Hurta Martin, Ing. - spoluřešitel
Husa Jakub, Ing., Ph.D. - spoluřešitel
Hussain Yasir - spoluřešitel
Chlebík Jakub, Ing. - spoluřešitel
Jaroš Jiří, doc. Ing., Ph.D. - spoluřešitel
Jaroš Marta, Ing., Ph.D. - spoluřešitel
Jawed Soyiba, Dr., MSc - spoluřešitel
Kadlubiak Kristián, Ing. - spoluřešitel
Kekely Lukáš, Ing., Ph.D. - spoluřešitel
Kekely Michal, Ing., Ph.D. - spoluřešitel
Klhůfek Jan, Ing. - spoluřešitel
Kocnová Jitka, Ing., Ph.D. - spoluřešitel
Kučera Jan, Ing., Ph.D. - spoluřešitel
Malik Aamir Saeed, prof., Ph.D. - spoluřešitel
Martínek Tomáš, doc. Ing., Ph.D. - spoluřešitel
Mrázek Vojtěch, Ing., Ph.D. - spoluřešitel
Olšák Ondřej, Ing. - spoluřešitel
Orsák Michal, Ing. - spoluřešitel
Pánek Richard, Ing., Ph.D. - spoluřešitel
Piňos Michal, Ing. - spoluřešitel
Růžička Richard, doc. Ing., Ph.D., MBA - spoluřešitel
Strnadel Josef, Ing., Ph.D. - spoluřešitel
Šimek Václav, Ing. - spoluřešitel
Šišmiš Lukáš, Ing. - spoluřešitel
Tisovčík Peter, Ing. - spoluřešitel
Vašíček Zdeněk, doc. Ing., Ph.D. - spoluřešitel
Zaheer Muhammad Asad - spoluřešitel

Ústav počítačových systémů
- interní (01.01.2023 - 31.12.2025)
Fakulta informačních technologií
- příjemce (01.01.2023 - 31.12.2025)

KEKELY, M.; KOŘENEK, J. Optimizing Packet Classification on FPGA. In PROCEEDINGS 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Tallinn: Institute of Electrical and Electronics Engineers, 2023. p. 7-12. ISBN: 979-8-3503-3277-3. ISSN: 2334-3133.
Detail

SEKANINA, L. Tutorial: Evolutionary Design Methods in Electronic Design Automation. IEEE 42nd International Conference on Computer Design (ICCD). Milano: IEEE Computer Society, 2024. p. 689-690. ISBN: 979-8-3503-8040-8.
Detail

AMIN, H.; ULLAH, R.; REZA, M.; MALIK, A. Single-trial extraction of event-related potentials (ERPs) and classification of visual stimuli by ensemble use of discrete wavelet transform with Huffman coding and machine learning techniques. Journal of NeuroEngineering and Rehabilitation, 2023, vol. 20, no. 1, p. 1-17. ISSN: 1743-0003.
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HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). Antwerp: Institute of Electrical and Electronics Engineers, 2023. p. 1-2. ISBN: 978-3-9819263-7-8.
Detail

LOJDA, J.; PÁNEK, R.; SEKANINA, L.; KOTÁSEK, Z. Automated Design and Usage of the Fault-Tolerant Dynamic Partial Reconfiguration Controller for FPGAs. Microelectronics Reliability, 2023, vol. 2023, no. 144, p. 1-16. ISSN: 0026-2714.
Detail

PÁNEK, R.; LOJDA, J. The Fault-tolerant Single-FPGA Systems with a Self-repair Reconfiguration Controller. In LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings. Quito: Institute of Electrical and Electronics Engineers, 2023. p. 104-107. ISBN: 978-1-6654-5705-7.
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MOINUDDIN, M.; ZERGUINE, A.; ARIF, M. A Weighted Gaussian Kernel Least Mean Square Algorithm. CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2023, vol. 42, no. 9, p. 5267-5288. ISSN: 0278-081X.
Detail

MAHRUKH, R.; SHAKIL, S.; MALIK, A. Sentiments analysis of fMRI using automatically generated stimuli labels under naturalistic paradigm. Scientific Reports, 2023, vol. 13, no. 1, p. 1-15. ISSN: 2045-2322.
Detail

CHLEBÍK, J.; JAROŠ, J. Evolutionary Optimization of a Focused Ultrasound Propagation Predictor Neural Network. GECCO 2023 Companion - Proceedings of the 2023 Genetic and Evolutionary Computation Conference Companion. Lisbon: Association for Computing Machinery, 2023. p. 635-638. ISBN: 979-8-4007-0120-7.
Detail

HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. Multi-objective Design of Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. Evo* 2023 -- Late-Breaking Abstracts Volume. Brno: 2023. p. 0-0.
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RŮŽIČKA, R.; ŠIMEK, V.; NEVORAL, J. Polymorphic RTL Computational Elements. Proceedings of the DSD 2023. Durres: IEEE Computer Society, 2023. p. 523-530. ISBN: 979-8-3503-4419-6.
Detail

SHAIKH, U.; SHAHZAIB, M.; SHAKIL, S.; BHATTI, F.; MALIK, A. Robust and Adaptive Terrain Classification and Gait Event Detection System. Heliyon, 2023, vol. 9, no. 11, p. 1-12. ISSN: 2405-8440.
Detail

ŠIŠMIŠ, L.; KOŘENEK, J. Analysis of TLS Prefiltering for IDS Acceleration. In Passive and Active Measurement 2023. Lecture Notes in Computer Science. Lecture Notes in Computer Science. Madrid: Springer Nature Switzerland AG, 2023. p. 85-109. ISBN: 978-3-031-28485-4. ISSN: 0302-9743.
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HUSA, J.; SEKANINA, L. Semantic Mutation Operator for Fast and Efficient Design of Bent Boolean Functions. Evo* 2023 -- Late-Breaking Abstracts Volume. Brno: 2023. p. 0-0.
Detail

PIŇOS, M.; MRÁZEK, V.; SEKANINA, L. Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. In 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Talinn: Institute of Electrical and Electronics Engineers, 2023. p. 45-50. ISBN: 979-8-3503-3277-3.
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JAROŠ, M.; JAROŠ, J. k-Dispatch: Enabling Cost-Optimized Biomedical Workflow Offloading. HPDC '24: Proceedings of the 33rd International Symposium on High-Performance Parallel and Distributed Computing. New York: Association for Computing Machinery, 2024. p. 358-360. ISBN: 979-8-4007-0413-0.
Detail

JAWED, S.; FAYE, I.; MALIK, A. Deep learning-based assessment model for Real-time identification of visual learners using Raw EEG. IEEE TRANSACTIONS ON NEURAL SYSTEMS AND REHABILITATION ENGINEERING, 2024, vol. 32, no. 1, p. 378-390. ISSN: 1558-0210.
Detail

BARDONEK, P.; ZACHARIÁŠOVÁ, M. Control Flow Analysis for Bottom-up Portable Models Creation. DVCon Europe 2023; Design and Verification Conference and Exhibition Europe. Mnichov: VDE VERLAG, 2023. p. 65-70. ISBN: 978-3-8007-6205-7.
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DENIZIAK, S.; SITEK, P.; JENIHHIN, M.; STEININGER, A.; SCHÖLZEL, M.; MRÁZEK, V. 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Kliece: Institute of Electrical and Electronics Engineers, 2024. p. 0-0. ISBN: 979-8-3503-5934-3.
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GOLDSCHMIDT, P.; KUČERA, J. Windower: Feature Extraction for Real-Time DDoS Detection Using Machine Learning. NOMS 2024-2024 IEEE Network Operations and Management Symposium. Seoul: Institute of Electrical and Electronics Engineers, 2024. p. 1-10. ISBN: 979-8-3503-2793-9.
Detail

MAJER, M.; HORKÝ, J.; VÁVRA, J.; JAROŠ, J.: riscv-sim; Web-Based Simulator of Superscalar RISC-V Processors. Zdrojové kódy: https://github.com/Sekky61/riscv-sim Živá instalace: https://sc-nas.fit.vutbr.cz/riscv-sim. URL: https://www.fit.vut.cz/research/product/834/. (software)
Detail

MRÁZEK, V.: autoax; autoAx: An Open-Source Automated Design Space Exploration Framework for Approximate Accelerators in FPGAs and ASICs. https://github.com/ehw-fit/autoax. URL: https://github.com/ehw-fit/autoax. (software)
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