Detail publikace

Hardware Architecture for the Fast Pattern Matching

KAŠTIL, J. KOŠAŘ, V. KOŘENEK, J.

Originální název

Hardware Architecture for the Fast Pattern Matching

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

As the speed of current computer networks in- creases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow.

Klíčová slova

pattern matching, intrussion detection system, regular expression, FPGA

Autoři

KAŠTIL, J.; KOŠAŘ, V.; KOŘENEK, J.

Rok RIV

2013

Vydáno

15. 4. 2013

Nakladatel

IEEE Computer Society

Místo

Brno

ISBN

978-1-4673-6133-0

Kniha

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

Strany od

120

Strany do

123

Strany počet

4

BibTex

@inproceedings{BUT103447,
  author="Jan {Kaštil} and Vlastimil {Košař} and Jan {Kořenek}",
  title="Hardware Architecture for the Fast Pattern Matching",
  booktitle="2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)",
  year="2013",
  pages="120--123",
  publisher="IEEE Computer Society",
  address="Brno",
  isbn="978-1-4673-6133-0"
}