Detail publikace

Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area

MIČULKA, L. STRAKA, M. KOTÁSEK, Z.

Originální název

Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used.

Klíčová slova

methodology, partial dynamic reconfiguration, relocation, synchronization, limited redundant space

Autoři

MIČULKA, L.; STRAKA, M.; KOTÁSEK, Z.

Rok RIV

2013

Vydáno

29. 3. 2013

Nakladatel

IEEE Computer Society

Místo

Santander

ISBN

978-0-7695-5074-9

Kniha

16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

Strany od

227

Strany do

234

Strany počet

8

BibTex

@inproceedings{BUT103518,
  author="Lukáš {Mičulka} and Martin {Straka} and Zdeněk {Kotásek}",
  title="Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area",
  booktitle="16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools",
  year="2013",
  pages="227--234",
  publisher="IEEE Computer Society",
  address="Santander",
  isbn="978-0-7695-5074-9"
}