Detail publikace

SWITCHED - CAPACITOR ADC WITH LOW POWER CONSUMPTION - BEHAVIOURAL MODELLING

HÁZE, J. VRBA, R. SKOČDOPOLE, M. FUJCIK, L.

Originální název

SWITCHED - CAPACITOR ADC WITH LOW POWER CONSUMPTION - BEHAVIOURAL MODELLING

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

A paper deals with 12-bit, low power switched- capacitor (SC) analog-todigital converter (ADC). Since the ADC will be used in portable applications the low power consumption is the key task for design. The paper focuses on block design of ADC and its behavioural modelling. The basic block topology design is also outlined. Techniques for avoiding of capacitor mismatch, clock feedthrough, finite gain and offset of Op-Amp etc. are utilized in the design.

Klíčová slova

A/D Converter, switched capacitors, low power, error correction, block diagram.

Autoři

HÁZE, J.; VRBA, R.; SKOČDOPOLE, M.; FUJCIK, L.

Rok RIV

2004

Vydáno

1. 12. 2004

Místo

Crete, Greece

ISBN

80-214-2819-8

Kniha

Socrates Workshop 2004. Intensive Training Programme in Electronic

Číslo edice

1

Strany od

162

Strany do

167

Strany počet

6

BibTex

@inproceedings{BUT11884,
  author="Jiří {Háze} and Radimír {Vrba} and Michal {Skočdopole} and Lukáš {Fujcik}",
  title="SWITCHED - CAPACITOR ADC WITH LOW POWER CONSUMPTION - BEHAVIOURAL MODELLING",
  booktitle="Socrates Workshop 2004. Intensive Training Programme in Electronic",
  year="2004",
  number="1",
  pages="6",
  address="Crete, Greece",
  isbn="80-214-2819-8"
}