Detail publikace

Low-latency AES encryption for High-Frequency Trading on FPGA

CÍBIK, P.

Originální název

Low-latency AES encryption for High-Frequency Trading on FPGA

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

This paper presents a Field Programmable Gate Array (FPGA) powered low--latency solution for secure communication with the stock exchange. It presents architecture design and optimization techniques used to ensure the required security level without impacting the latency, which is the most critical domain in High-Frequency Trading (HFT). The National Stock Exchange of India (NSE) chose Advanced Encryption Standard (AES) with 256 bit key length in Galoise-Counter Mode (GCM) as the encryption algorithm for Non-NEAT Front End (NNF) connections.

Klíčová slova

Field-Programmable Gate Array;FPGA;High-Frequency Trading;HFT;National Stock Exchange of India;NSE;Cryptography;Hardware acceleration;VHDL;Encryption;Decryption;AES;GCM

Autoři

CÍBIK, P.

Vydáno

23. 4. 2024

ISBN

978-80-214-6231-1

Kniha

Proceedings I of the 30th Conference STUDENT EEICT 2024

Edice

Assoc. Prof. Vítězslav Novák

Číslo edice

1

Strany od

236

Strany do

240

Strany počet

5

URL

https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2024_sbornik_1.pdf

BibTex

@inproceedings{BUT188499,
  author="Peter {Cíbik}",
  title="Low-latency AES encryption for High-Frequency Trading on FPGA",
  booktitle="Proceedings I of the 30th Conference STUDENT EEICT 2024",
  year="2024",
  series="Assoc. Prof. Vítězslav Novák",
  number="1",
  pages="236--240",
  isbn="978-80-214-6231-1",
  url="https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2024_sbornik_1.pdf"
}