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BLACK, C. JEŘÁBEK, J. ŠOTNER, R. FREEBORN, T.
Originální název
Emulation of Fractional-Order Impedance with α=0.5 using MOSFET Revised RC-Ladder Topology
Typ
článek ve sborníku ve WoS nebo Scopus
Jazyk
angličtina
Originální abstrakt
Approximations of fractional-order capacitors are widely implemented using passive RC ladder topologies. One alternative to this approach is to replace resistors in these topologies with MOSFET devices biased to operate as resistors. To validate this approach, fractional-order capacitors with alpha = 0.5 are approximated (with a +/- 1 degrees phase error target) with MOSFET revised ladder topologies in parallel and series configurations. The measured phases of these realized approximations had average differences of 0.7 degrees and 3.1 degrees for the parallel and series cases, respectively, with maximum differences of 1.7 degrees and 13.3 degrees for the frequency band from 100 Hz to 10 kHz.
Klíčová slova
Frequency Band; Parallel Configuration; Parallel Case; Series Configuration; Solid Line; Operation Mode; Ideal Value; Bias Voltage; Circuit Design; Phase Characteristics; Keysight; Physical Reality; Ideal Characteristics; Impedance Phase; Gate-source Voltage; Variable Resistor; Circuit Impedance; Parallel Topology
Autoři
BLACK, C.; JEŘÁBEK, J.; ŠOTNER, R.; FREEBORN, T.
Vydáno
24. 3. 2024
Nakladatel
IEEE
Místo
NEW YORK
ISBN
979-8-3503-1710-7
Kniha
IEEE SoutheastCon-Proceedings
Strany od
1223
Strany do
1228
Strany počet
6
BibTex
@inproceedings{BUT189329, author="Chloe {Black} and Jan {Jeřábek} and Roman {Šotner} and Todd {Freeborn}", title="Emulation of Fractional-Order Impedance with α=0.5 using MOSFET Revised RC-Ladder Topology", booktitle="IEEE SoutheastCon-Proceedings", year="2024", pages="1223--1228", publisher="IEEE", address="NEW YORK", doi="10.1109/SOUTHEASTCON52093.2024.10500247", isbn="979-8-3503-1710-7" }