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MATOUŠEK, P., SMRČKA, A., VOJNAR, T.
Originální název
High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design
Typ
článek ve sborníku ve WoS nebo Scopus
Jazyk
angličtina
Originální abstrakt
The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too.
Klíčová slova
formal analysis and verification, timed automata, parametric analysis, FPGA, hardware, computer networks
Autoři
Rok RIV
2005
Vydáno
3. 10. 2005
Nakladatel
Springer Verlag
Místo
Berlin
ISBN
978-3-540-29105-3
Kniha
Correct Hardware Design and Verification Methods
Edice
Lecture Notes in Computer Science 3725/2005
ISSN
0302-9743
Periodikum
Lecture Notes in Computer Science
Ročník
Číslo
3725
Stát
Spolková republika Německo
Strany od
371
Strany do
375
Strany počet
5
URL
http://www.fit.vutbr.cz/~vojnar/Publications/smv-charme-05.ps.gz
BibTex
@inproceedings{BUT30742, author="Petr {Matoušek} and Aleš {Smrčka} and Tomáš {Vojnar}", title="High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design", booktitle="Correct Hardware Design and Verification Methods", year="2005", series="Lecture Notes in Computer Science 3725/2005", journal="Lecture Notes in Computer Science", volume="2005", number="3725", pages="371--375", publisher="Springer Verlag", address="Berlin", isbn="978-3-540-29105-3", issn="0302-9743", url="http://www.fit.vutbr.cz/~vojnar/Publications/smv-charme-05.ps.gz" }