Detail publikace

Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation

SOVA, V. GREPL, R.

Originální název

Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

This paper presents Hardware in the Loop (HIL) simulation of the BLDC motor used in aerospace applications. Due to a high frequency driving signals and a high dynamics of the electrical part of the BLDC motor, the utilization of FPGA is necessary. The algorithm is distributed between the CPU and the FPGA and targeted to dSPACE modular hardware.

Klíčová slova

BLDC, HIL, FPGA

Autoři

SOVA, V.; GREPL, R.

Rok RIV

2013

Vydáno

9. 10. 2013

Nakladatel

Springer International Publishing

Místo

Cham, Heidelberg, New York, Dordrecht, London

ISBN

978-3-319-02293-2

Kniha

Mechatronics 2013: Recent Technological and Scientific Advances

Edice

Mechatronics

Strany od

135

Strany do

142

Strany počet

8

BibTex

@inproceedings{BUT106474,
  author="Václav {Sova} and Robert {Grepl}",
  title="Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation",
  booktitle="Mechatronics 2013: Recent Technological and Scientific Advances",
  year="2013",
  series="Mechatronics",
  pages="135--142",
  publisher="Springer International Publishing",
  address="Cham, Heidelberg, New York, Dordrecht, London",
  doi="10.1007/978-3-319-02294-9\{_}84",
  isbn="978-3-319-02293-2"
}