Efficient Implementation of Clock and Data Recovery

článek ve sborníku ve WoS nebo Scopus

angličtina

Clock and data recovery (CDR) is very common operation in modern communication systems. Data are usually transmitted without corresponding clock signal because it is inefficient and sometimes even impossible. Then it is necessary to recover a replica of the original clock signal on the receiver side. The replicated clock signal is derived from the incoming data signal and must have the same frequency and phase as the original one (rising edge of the clock must appear in the middle of the data bit). CDR can be managed in several ways depending strongly on the desired data rate. This paper describes possible solutions of CDR at data rates from about 100 Mb/s to several hundreds of Mb/s (the lower limit is only in terms of cost efficiency, not in capabilities, [3]).

Clock recovery, FPGA, VHDL, CDR

KUBÍČEK, M.; KOVÁČ, M.

2007

1. 1. 2007

University of Miskolc

University of Miskolc, Hungary

978-963-661-783-7

Proceedings of the 6th International Conference of PhD Students

1

289

292

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