Detail publikace

Serial IIR Filter Generator for ASIC

PRISTACH, M. FUJCIK, L.

Originální název

Serial IIR Filter Generator for ASIC

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

The paper presents an infinite impulse response (IIR) filter generator for application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. This architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. A software in C++ language for automatic filter generation was written. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for filter verification from the filter specification file.

Klíčová slova

application specific integration circuits, hardware description language, infinite impulse response filter, multiply and accumulate unit

Autoři

PRISTACH, M.; FUJCIK, L.

Rok RIV

2012

Vydáno

28. 6. 2012

Nakladatel

Vysoké učení technické v Brně

Místo

Brno

ISBN

978-80-214-4539-0

Kniha

Electronic Devices and Systems IMAPS CS International Conference 2011 Proceedings

Edice

první

Strany od

219

Strany do

223

Strany počet

5

BibTex

@inproceedings{BUT93774,
  author="Marián {Pristach} and Lukáš {Fujcik}",
  title="Serial IIR Filter Generator for ASIC",
  booktitle="Electronic Devices and Systems IMAPS CS International Conference 2011 Proceedings",
  year="2012",
  series="první",
  pages="219--223",
  publisher="Vysoké učení technické v Brně",
  address="Brno",
  isbn="978-80-214-4539-0"
}