Project detail

Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification

Duration: 01.03.2012 — 30.11.2015

Funding resources

Ministerstvo školství, mládeže a tělovýchovy ČR - COST CZ (2011-2017)

- whole funder (2012-03-01 - 2015-11-30)

On the project

Projekt má tyto cíle a kroky řešení: 1) Vývoj a implementace nové metodiky návrh systémů odolných proti poruchám do FPGA včetně detekce poruch, lokalizace poruchy, rekonfigurace a synchronizace po rekonfiguraci. 2)  Vývoj a implementaci nové metodiky pro automatické generování diagnostických komponent pro on-line testování systémů implementovaných do FPGA. 3) Vývoj technik pro ověření kvality návrhu systémů odolných proti poruchám, vývoj injektoru SEU poruch použitelné pro rekonfigurovatelné platformy.  4) Experimentální ověření metodiky. 5) Analýza výsledků projektu.  

Description in English
The project has these goals and steps of research: 1) Development and implementation of a new methodology for fault tolerant systems design into FPGA including error detection, faults localization, reconfiguration and synchronization after reconfiguration process. 2) Development and implementation of a new methodology for automated generation of diagnostic resources for on-line testing of FPGA based systems. 3) Development of techniques for the verification of fault tolerant systems quality together with SEU injector tool to be used for reconfigurable platforms. 4) Experimental evaluation of the methodology. 5) The analysis of project results.

Keywords
číslicový obvod, hlídací obvody, systémy odolné proti poruchám, SEU, simulace, generátor, testování, verifikace, FPGA, rekonfigurace, řadič, metodika

Key words in English
digital circuit, checker, fault tolerant system, SEU, simulation, generator, testing, verification, FPGA, reconfiguration, controller, methodology

Mark

LD12036

Default language

Czech

People responsible

Krčma Martin, Ing., Ph.D. - fellow researcher
Szurman Karel, Ing., Ph.D. - fellow researcher
Kotásek Zdeněk, doc. Ing., CSc. - principal person responsible

Units

Department of Computer Systems
- beneficiary (2011-12-20 - 2015-11-30)

Results

STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.; MIČULKA, L. Fault Tolerant System Design and SEU Injection based Testing. Microprocessors and Microsystems, 2013, vol. 2013, no. 37, p. 155-173. ISSN: 0141-9331.
Detail

PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Radiation Impact on Mechanical Application Driven by FPGA-based Controller. Proceedings of The Fourth Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015. p. 13-16.
Detail

STRNADEL, J.; SLIMAŘÍK, F. On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. Proceedings of the 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Pistacaway: IEEE Computer Society, 2012. p. 272-279. ISBN: 978-0-7695-4798-5.
Detail

KAŠTIL, J.; STRAKA, M.; MIČULKA, L.; KOTÁSEK, Z. Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012. p. 250-257. ISBN: 978-0-7695-4798-5.
Detail

STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Methodology for Reliability Analysis of FPGA-based Fault Tolerant Systems. CSE'2012 International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2012. p. 146-153. ISBN: 978-80-8143-049-7.
Detail

MIČULKA, L.; KOTÁSEK, Z. Design Sychronization after Partial Dynamic Reconfiguration of Fault Tolerant System. 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012. p. 20-21. ISBN: 978-3-902457-33-2.
Detail

ZACHARIÁŠOVÁ, M. Acceleration of Functional Verification in the Development Cycle of Hardware Systems. Počítačové architektury a diagnostika. Praha: Czech Technical University, 2012. p. 73-78. ISBN: 978-80-01-05106-1.
Detail

MIČULKA, L. Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA. Počítačové architektury & diagnostika 2012. Praha: Fakulta informačních technologií ČVUT, 2012. s. 109-115. ISBN: 978-80-01-05106-1.
Detail

STRAKA, M.; MIČULKA, L.; KAŠTIL, J.; KOTÁSEK, Z. Test Platform for Fault Tolerant Systems Design Qualities Verification. 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Tallin: IEEE Computer Society, 2012. p. 336-341. ISBN: 978-1-4673-1185-4.
Detail

ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Universal Pseudo-random Generation of Assembler Codes for Processors. Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015. p. 70-73.
Detail

PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. Microprocessors and Microsystems, 2015, vol. 39, no. 8, p. 1215-1230. ISSN: 0141-9331.
Detail

STRNADEL, J. Plánování úloh v systémech RT - V: zvyšování provozuschopnosti systémů. Automa, 2013, roč. 19, č. 2, s. 46-49. ISSN: 1210-9592.
Detail

ZACHARIÁŠOVÁ, M.; BOLCHINI, C.; KOTÁSEK, Z. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Karlovy Vary: IEEE Computer Society, 2013. p. 275-278. ISBN: 978-1-4673-6133-0.
Detail

MIČULKA, L.; KOTÁSEK, Z. Synchronization Technique for TMR System After Dynamic Reconfiguration on FPGA. The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2013). Avignon: Politecnico di Milano, 2013. p. 53-56. ISBN: 978-2-11-129175-1.
Detail

MIČULKA, L.; STRAKA, M.; KOTÁSEK, Z. Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area. 16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Santander: IEEE Computer Society, 2013. p. 227-234. ISBN: 978-0-7695-5074-9.
Detail

ZACHARIÁŠOVÁ, M.; BOLCHINI, C.; KOTÁSEK, Z. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. Proceedings of The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Avignon: COST, European Cooperation in Science and Technology, 2013. p. 35-38. ISBN: 978-2-11-129175-1.
Detail

MIČULKA, L. Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA. Počítačové architektury & diagnostika 2013. Plzeň: Západočeská univerzita v Plzni, 2013. s. 63-68. ISBN: 978-80-261-0270-0.
Detail

SZURMAN, K. Fault Tolerant CAN Bus Control System Implemented into FPGA and its synchronization after failure and recovery. Počítačové architektury & diagnostika 2013. Plzeň: University of West Bohemia in Pilsen, 2013. p. 21-26. ISBN: 978-1-4673-6136-1.
Detail

ZACHARIÁŠOVÁ, M. New Methods for Increasing Efficiency and Speed of Functional Verification. Počítačové architektury a diagnostika PAD 2013. Plzeň: University of West Bohemia in Pilsen, 2013. p. 111-116. ISBN: 978-80-261-0270-0.
Detail

KOTÁSEK, Z.; MIČULKA, L. Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. p. 171-174. ISBN: 978-0-7695-5074-9.
Detail

STRNADEL, J.; POKORNÝ, M. Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. In Proceedings of the 2014 17th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2014. p. 333-340. ISBN: 978-1-4799-5793-4.
Detail

PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Complex Control System for Testing Fault-Tolerance Methodologies. Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Dresden: COST, European Cooperation in Science and Technology, 2014. p. 24-27. ISBN: 978-2-11-129175-1.
Detail

ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Solving of Constraint Satisfaction Problem. Proceedings of the 20th Conference STUDENT EEICT 2014. Volume 3. Brno: Faculty of Information Technology BUT, 2014. p. 291-295. ISBN: 978-80-214-4924-4.
Detail

PODIVÍNSKÝ, J. Testing Fault-Tolerance Properties in FPGA based Electro-mechanical Applications. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. p. 13-18. ISBN: 978-80-7494-027-9.
Detail

PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 312-319. ISBN: 978-1-4799-5793-4.
Detail

SZURMAN, K.; MIČULKA, L.; KOTÁSEK, Z. State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 704-707. ISBN: 978-1-4799-5793-4.
Detail

SZURMAN, K. Synchronization Methodology for Fault Tolerant System Recovery After Its Failure. Počítačové architektury & diagnostika 2014. Malá Skála: Liberec University of Technology, 2014. p. 111-116. ISBN: 978-80-7494-027-9.
Detail

MATUŠOVÁ, L.; KAŠTIL, J.; KOTÁSEK, Z. Automatic Construction of On-line Checking Circuits Based on Finite Automata. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 326-332. ISBN: 978-0-7695-5074-9.
Detail

ZACHARIÁŠOVÁ, M. Application of Evolutionary Computing for Optimization of Functional Verification. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. p. 135-140. ISBN: 978-80-7494-027-9.
Detail

ČEKAN, O. Universal Generation of Test Vectors for Functional Verification. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. p. 44-49. ISBN: 978-80-7494-027-9.
Detail

SZURMAN, K.; MIČULKA, L.; KOTÁSEK, Z. Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems. In 9th IEEE International Conference on Computer Engineering and Systems. Káhira: IEEE Computer Society, 2014. p. 231-236. ISBN: 978-1-4799-6594-6.
Detail

STRNADEL, J.; SLIMAŘÍK, F. Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems. Computing and Informatics, 2014, vol. 33, no. 4, p. 757-782. ISSN: 1335-9150.
Detail

PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; ČEKAN, O.; KOTÁSEK, Z. FPGA Prototyping and Accelerated Verification of ASIPs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. p. 145-148. ISBN: 978-1-4799-6780-3.
Detail

ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Automation and Optimization of Coverage-driven Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 87-94. ISBN: 978-1-4673-8035-5.
Detail

ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Software Fault Tolerance: the Evaluation by Functional Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 284-287. ISBN: 978-1-4673-8035-5.
Detail

ČEKAN, O. Principy generování verifikačních stimulů. Počítačové architektury a diagnostika PAD 2015. Zlín: Fakulta aplikované informatiky, Univerzita Tomáše Bati ve Zlíně, 2015. s. 13-18. ISBN: 978-80-7454-522-1.
Detail

KRČMA, M.; KOTÁSEK, Z.; KAŠTIL, J. Fault Tolerant Field Programmable Neural Networks. In 1st IEEE Nordic Circuits and Systems (NORCAS) Conference. Oslo: IEEE Computer Society, 2015. p. 1-4. ISBN: 978-1-4673-6575-8.
Detail

KRČMA, M. FPNN - neuronové sítě v FPGA. Počítačové architektury a diagnostika PAD 2015. Zlín: Univerzita Tomáše Bati ve Zlíně, 2015. s. 81-86. ISBN: 978-80-7454-522-1.
Detail

STRAKA, M.: ArchGenCheckGen; Nástroje pro generování odolných architektur a hlídacích obvodů z jazyka VHDL. http://www.fit.vutbr.cz/research/grants/index.php.cs?id=618. URL: http://www.fit.vutbr.cz/research/grants/index.php.cs?id=618. (software)
Detail

STRAKA, M.; KAŠTIL, J.: GPDRC; GPDRC: Generic partial dynamic reconfiguration controller. http://www.fit.vutbr.cz/research/grants/index.php.cs?id=618. URL: http://www.fit.vutbr.cz/research/grants/index.php.cs?id=618. (software)
Detail

KAŠTIL, J.: SEUInjector; External SEU injector. http://eva.fit.vutbr.cz/~xkasti00/soubory/injector.tcl. URL: http://eva.fit.vutbr.cz/~xkasti00/soubory/injector.tcl. (software)
Detail

Responsibility: Kotásek Zdeněk, doc. Ing., CSc.