Projekt má tyto cíle a kroky řešení: 1) Vývoj a implementace nové metodiky návrh systémů odolných proti poruchám do FPGA včetně detekce poruch, lokalizace poruchy, rekonfigurace a synchronizace po rekonfiguraci. 2)  Vývoj a implementaci nové metodiky pro automatické generování diagnostických komponent pro on-line testování systémů implementovaných do FPGA. 3) Vývoj technik pro ověření kvality návrhu systémů odolných proti poruchám, vývoj injektoru SEU poruch použitelné pro rekonfigurovatelné platformy.  4) Experimentální ověření metodiky. 5) Analýza výsledků projektu.  

Description in English
The project has these goals and steps of research: 1) Development and implementation of a new methodology for fault tolerant systems design into FPGA including error detection, faults localization, reconfiguration and synchronization after reconfiguration process. 2) Development and implementation of a new methodology for automated generation of diagnostic resources for on-line testing of FPGA based systems. 3) Development of techniques for the verification of fault tolerant systems quality together with SEU injector tool to be used for reconfigurable platforms. 4) Experimental evaluation of the methodology. 5) The analysis of project results.

Keywords
číslicový obvod, hlídací obvody, systémy odolné proti poruchám, SEU, simulace, generátor, testování, verifikace, FPGA, rekonfigurace, řadič, metodika

Key words in English
digital circuit, checker, fault tolerant system, SEU, simulation, generator, testing, verification, FPGA, reconfiguration, controller, methodology

LD12036

Czech

Kotásek Zdeněk, doc. Ing., CSc. - principal person responsible
Krčma Martin, Ing., Ph.D. - fellow researcher
Szurman Karel, Ing., Ph.D. - fellow researcher

Department of Computer Systems
- responsible department (20.12.2011 - not assigned)
Dependable Digital Systems Research Group
- internal (20.12.2011 - 30.11.2015)
Department of Computer Systems
- beneficiary (20.12.2011 - 30.11.2015)

SZURMAN, K.; KAŠTIL, J.; STRAKA, M.; KOTÁSEK, Z. Fault Tolerant CAN Bus Control System Implemented into FPGA. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013. Karlovy Vary: IEEE Computer Society, 2013. p. 289-292. ISBN: 978-1-4673-6136-1.
Detail

ZACHARIÁŠOVÁ, M.; LENGÁL, O. Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures. Lecture Notes in Computer Science, 2012, vol. 2013, no. 7857, p. 266-273. ISSN: 0302-9743.
Detail

ZACHARIÁŠOVÁ, M.; LENGÁL, O. Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures. FIT-TR-2012-03, Brno: Faculty of Information Technology BUT, 2012. p. 0-0.
Detail

PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Radiation Impact on Mechanical Application Driven by FPGA-based Controller. Proceedings of The Fourth Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015. p. 13-16.
Detail

ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Universal Pseudo-random Generation of Assembler Codes for Processors. Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015. p. 70-73.
Detail

STRAKA, M.: ArchGenCheckGen; Nástroje pro generování odolných architektur a hlídacích obvodů z jazyka VHDL. http://www.fit.vutbr.cz/research/grants/index.php.cs?id=618. URL: http://www.fit.vutbr.cz/research/grants/index.php.cs?id=618. (software)
Detail

STRAKA, M.; KAŠTIL, J.: GPDRC; GPDRC: Řadič částečné dynamické rekonfigurace pro odolné architektury. http://www.fit.vutbr.cz/research/grants/index.php.cs?id=618. URL: http://www.fit.vutbr.cz/research/grants/index.php.cs?id=618. (software)
Detail

PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. Microprocessors and Microsystems, 2015, vol. 39, no. 8, p. 1215-1230. ISSN: 0141-9331.
Detail

KRČMA, M. FPNN - neuronové sítě v FPGA. Počítačové architektury a diagnostika PAD 2015. Zlín: Univerzita Tomáše Bati ve Zlíně, 2015. s. 81-86. ISBN: 978-80-7454-522-1.
Detail

KRČMA, M.; KOTÁSEK, Z.; KAŠTIL, J. Fault Tolerant Field Programmable Neural Networks. In 1st IEEE Nordic Circuits and Systems (NORCAS) Conference. Oslo: IEEE Computer Society, 2015. p. 1-4. ISBN: 978-1-4673-6575-8.
Detail

ČEKAN, O. Principy generování verifikačních stimulů. Počítačové architektury a diagnostika PAD 2015. Zlín: Fakulta aplikované informatiky, Univerzita Tomáše Bati ve Zlíně, 2015. s. 13-18. ISBN: 978-80-7454-522-1.
Detail

ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Software Fault Tolerance: the Evaluation by Functional Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 284-287. ISBN: 978-1-4673-8035-5.
Detail

ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Automation and Optimization of Coverage-driven Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 87-94. ISBN: 978-1-4673-8035-5.
Detail

PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; ČEKAN, O.; KOTÁSEK, Z. FPGA Prototyping and Accelerated Verification of ASIPs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. p. 145-148. ISBN: 978-1-4799-6780-3.
Detail

STRNADEL, J.; SLIMAŘÍK, F. Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems. Computing and Informatics, 2014, vol. 33, no. 4, p. 757-782. ISSN: 1335-9150.
Detail

SZURMAN, K.; MIČULKA, L.; KOTÁSEK, Z. Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems. In 9th IEEE International Conference on Computer Engineering and Systems. Káhira: IEEE Computer Society, 2014. p. 231-236. ISBN: 978-1-4799-6594-6.
Detail

ČEKAN, O. Universal Generation of Test Vectors for Functional Verification. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. p. 44-49. ISBN: 978-80-7494-027-9.
Detail

ZACHARIÁŠOVÁ, M. Application of Evolutionary Computing for Optimization of Functional Verification. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. p. 135-140. ISBN: 978-80-7494-027-9.
Detail

MATUŠOVÁ, L.; KAŠTIL, J.; KOTÁSEK, Z. Automatic Construction of On-line Checking Circuits Based on Finite Automata. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 326-332. ISBN: 978-0-7695-5074-9.
Detail

SZURMAN, K. Synchronization Methodology for Fault Tolerant System Recovery After Its Failure. Počítačové architektury & diagnostika 2014. Malá Skála: Liberec University of Technology, 2014. p. 111-116. ISBN: 978-80-7494-027-9.
Detail

Responsibility: Kotásek Zdeněk, doc. Ing., CSc.