Project detail

Tools for AI-enhanced Security Verification of Cryptographic Devices

Duration: 01.01.2022 — 31.12.2025

Funding resources

Ministerstvo vnitra ČR - Strategická podpora rozvoje bezpečnostního výzkumu ČR 2019–2025 (IMPAKT 1) PODPROGRAMU 1 SPOLEČNÉ VÝZKUMNÉ PROJEKTY (BV IMP1/2VS)

- whole funder (2021-12-01 - not assigned)

On the project

Description in English
The project addresses current shortage of tools for the analysis and verification of security certifications for devices used in cybersecurity. In particular, for hardware devices implementing cryptographic algorithms, such as smartcards, it is currently difficult in the Czech Republic to verify the declared levels of security reliably. That prevents performing risk analysis of systems based on these devices and, therefore, their use by national security agencies and critical information infrastructures. The project will deliver novel hardware and software tools based on the AI principles that will be usable for specific steps in automated verification of device security with respect to either declared certification or manufacturer’s/vendor’s statement.

Key words in English
Cybersecurity, cryptography, certification, artificial intelligence, analysis, security evaluation

Mark

VJ02010010

Default language

Czech

People responsible

Martinásek Zdeněk, doc. Ing., Ph.D. - fellow researcher
Hajný Jan, prof. Ing., Ph.D. - principal person responsible

Units

Department of Telecommunications
- beneficiary (2021-04-15 - not assigned)

Results

JEDLIČKA, P.; HAJNÝ, J. VHDL-based implementation of CRYSTALS-Kyber components on FPGA. In Proceedings II of the 28th Conference STUDENT EEICT 2022 Selected Papers. 1st. Brno: Brno University of Technology, Faculty of Electrical Engineering and Communication, 2022. p. 297-301. ISBN: 978-80-214-6030-0.
Detail

MARTINÁSEK, Z.; MALINA, L.; HAJNÝ, J.; JEDLIČKA, P.; GERLICH, T. Postup a výzkum týmu VUT v 2022: Analýza kryptografických primitiv na FPGA, bezpečnost, návrh testbedu. 2022. s. 1-18.
Detail

JEDLIČKA, P.; MALINA, L.; SOCHA, P.; GERLICH, T.; MARTINÁSEK, Z.; HAJNÝ, J. On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography. In ARES '22: Proceedings of the 17th International Conference on Availability, Reliability and Security. Vienna, Austria: ACM, 2022. p. 1-9. ISBN: 978-1-4503-9670-7.
Detail

HAJNÝ, J.; MARTINÁSEK, Z.; MALINA, L.; JEDLIČKA, P.; ŠVENDA, P.; NOVOTNÝ, M. Prezentace z Workshopu SecTools 2023. 2023.
Detail

HAJNÝ, J.; MARTINÁSEK, Z.; MALINA, L.; GERLICH, T.; ŠVENDA, P.; NOVOTNÝ, M. Prezentace z Workshopu SecTools 2024. 2024.
Detail

GERLICH, T.; KANDI, A.; BAKSI, A.; MARTINÁSEK, Z.; GUILLEY, S.; GAN, P.; BREIER, J.; CHATTOPADHYAY, A.; BHASIN, S.; SHRIVASTWA, R. Hardware Implementation of ASCON. NIST, 2023. p. 1-14.
Detail

BREIER, J.; HOU, X.; KOVAČEVIĆ, M. Another Look at Side-Channel-Resistant Encoding Schemes. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2024, vol. 32, no. 8, p. 1559-1563. ISSN: 1557-9999.
Detail

KANDI, A.; BAKSI, A.; GAN, P.; GUILLEY, S.; GERLICH, T.; BREIER, J.; CHATTOPADHYAY, A.; SHRIVASTWA, R.; MARTINÁSEK, Z.; BHASIN, S. Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation. In 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE Computer Society Annual Symposium on VLSI proceedings. Knoxville, Tennessee, USA: IEEE Computer Society, 2024. p. 307-312. ISBN: 979-8-3503-5412-6. ISSN: 2159-3477.
Detail

HAJNÝ, J.; MARTINÁSEK, Z.; MALINA, L.; GERLICH, T.; ŠVENDA, P.; NOVOTNÝ, M.: Workshop SecTools 2024. Praha (04.12.2024)
Detail

HAJNÝ, J.; MALINA, L.; MARTINÁSEK, Z.; JEDLIČKA, P.; ŠVENDA, P.; NOVOTNÝ, M.: Workshop SecTools 2023. Praha (18.09.2023)
Detail

Responsibility: Hajný Jan, prof. Ing., Ph.D.