Publications

• 2023

  FIEDOR, J.; KŘENA, B.; SMRČKA, A.; VAŠÍČEK, O.; VOJNAR, T. Integrating OSLC Services into Eclipse. In Computer Aided Systems Theory - EUROCAST 2022. Lecture Notes in Computer Science. Las Palmas de Gran Canaria: Springer International Publishing, 2023. p. 240-249. ISBN: 978-3-031-25311-9.
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  SMRČKA, A.; ROZSÍVAL, M. NetLoiter: A Tool for Automated Testing of Network Applications using Fault-injection. In Proceedings - 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops Volume, DSN-W 2023. Porto: Institute of Electrical and Electronics Engineers, 2023. p. 207-210. ISBN: 979-8-3503-2543-0.
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  HRUŠKA, M.; FIEDOR, T.; SMRČKA, A. Orchestrating Digital Twins for Distributed Manufacturing Execution Systems. In Computer Aided Systems Theory - EUROCAST 2022. Lecture Notes in Computer Science. Zurich: Springer International Publishing, 2023. p. 223-231. ISBN: 978-3-031-25311-9.
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  SMRČKA, A.; SANGCHOOLIE, B.; EMANUELE, M.; VARA, J.; FARRELL, M.; BARBOSA, R.; BAGLUM, C.; YAYAN, U.; ERGUN, S.; KANAK, A. Towards an extensive set of criteria for safety and cyber-security evaluation of cyber-physical systems [version 1; peer review: 2 approved]. 2023, vol. 3, no. 219, p. 1-21. ISSN: 2732-5121.
  Detail

• 2022

  BAUER, T.; AGIRRE, J.; FÜRCHO, D.; HERZNER, W.; HRUŠKA, B.; KARACA, M.; PEREIRA, D.; PROENÇA, J.; SCHLICK, R.; SICHER, R.; SMRČKA, A.; YAYAN, U.; SANGCHOOLIE, B. Cross-domain Modelling of Verification and Validation Workflows in the Large Scale European Research Project VALU3S Invited Paper. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Lecture Notes in Computer Science. Cham: 2022. p. 368-382.
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  VAŠÍČEK, O.; FIEDOR, J.; KRATOCHVÍLA, T.; KŘENA, B.; SMRČKA, A.; VOJNAR, T. Unite: An Adapter for Transforming Analysis Tools to Web Services via OSLC. In ESEC/FSE 2022: Proceedings of the 30th ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering. Singapore: Association for Computing Machinery, 2022. p. 1408-1418. ISBN: 978-1-4503-9413-0.
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  CHARVÁT, L.; SMRČKA, A.; VOJNAR, T. Utilizing parametric systems for detection of pipeline hazards. International Journal on Software Tools for Technology Transfer, 2022, vol. 2020, no. 1, p. 1-28. ISSN: 1433-2779.
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• 2021

  PEREIRA, D.; SANGCHOOLIE, B.; SMRČKA, A.; BARBOSA, R.; ESNAOLA, M.; GIANTAMIDIS, G.; SCHLICK, R.; YAZICI, A. The VALU3S ECSEL project: Verification and validation of automated systems safety and security. Microprocessors and Microsystems, 2021, vol. 87, no. 104349, p. 1-18. ISSN: 0141-9331.
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• 2020

  SANGCHOOLIE, B.; BECKER, H.; KANAK, A.; POMANTE, L.; SCHLICK, R.; SMRČKA, A.; BARBOSA, R.; ESNAOLA, M.; FERRARI, E.; GIANTAMIDIS, G.; PEREIRA, D.; YAZICI, A.; FOLKESSON, P. The VALU3S ECSEL Project: Verification and Validation of Automated Systems Safety and Security. In 2020 23rd Euromicro Conference on Digital System Design (DSD 2020). Krajn: Institute of Electrical and Electronics Engineers, 2020. p. 352-359. ISBN: 978-1-7281-9535-3.
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• 2018

  FIEDOR, J.; MUŽIKOVSKÁ, M.; SMRČKA, A.; VAŠÍČEK, O.; VOJNAR, T. Advances in the ANaConDA Framework for Dynamic Analysis and Testing of Concurrent C/C++ Programs. In Proceedings of 27th ACM SIGSOFT International Symposium on Software Testing and Analysis. New York: Association for Computing Machinery, 2018. p. 356-359. ISBN: 978-1-4503-5699-2.
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• 2017

  FIEDOR, J.; VOJNAR, T.; SMRČKA, A.; DIAS, R.; FERREIRA, C.; LOURENCO, J.; SOUSA, D. Verifying Concurrent Programs Using Contracts. In 2017 IEEE International Conference on Software Testing, Verification and Validation (ICST). Tokyo: Institute of Electrical and Electronics Engineers, 2017. p. 196-206. ISBN: 978-1-5090-6032-0.
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• 2016

  CHARVÁT, L.; SMRČKA, A.; VOJNAR, T. Hades: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems. In Proceedings 11th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS 2016). Electronic Proceedings in Theoretical Computer Science, EPTCS. Electronic Proceedings in Theoretical Computer Science. Brno: Faculty of Informatics MU, 2016. p. 87-93. ISBN: 978-80-210-8362-2. ISSN: 2075-2180.
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• 2015

  CHARVÁT, L.; SMRČKA, A.; VOJNAR, T. Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems. Proceedings of the 15th International Conference on Computer Aided Systems Theory (EUROCAST 2015). Las Palmas de Grand Canaria: The Universidad de Las Palmas de Gran Canaria, 2015. p. 193-194. ISBN: 978-84-606-5438-4.
  Detail

  CHARVÁT, L.; SMRČKA, A.; VOJNAR, T. Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems. In Computer Aided Systems Theory - EUROCAST 2015. Lecture Notes in Computer Science. Lecture Notes in Computer Science. Zurich: Springer International Publishing, 2015. p. 605-614. ISBN: 978-3-319-27340-2. ISSN: 0302-9743.
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• 2014

  CHARVÁT, L.; SMRČKA, A.; VOJNAR, T. Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors. In Proceedings of 15th International Workshop on Microprocessor Test and Verification (MTV 2014). Austin, TX: IEEE Computer Society, 2014. p. 83-89. ISBN: 978-1-4673-6858-2.
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• 2013

  CHARVÁT, L.; SMRČKA, A.; VOJNAR, T. An Abstraction of Multi-Port Memories with Arbitrary Addressable Units. Proceedings of the 14th Computer Aided Systems Theory. Las Palmas de Grand Canaria: The Universidad de Las Palmas de Gran Canaria, 2013. p. 254-255. ISBN: 978-84-695-6971-9.
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  CHARVÁT, L.; SMRČKA, A.; VOJNAR, T. An Abstraction of Multi-Port Memories with Arbitrary Addressable Units. Computer Aided Systems Theory - EUROCAST 2013. Lecture Notes in Computer Science. Berlin Heidelberg: Springer Verlag, 2013. p. 460-468. ISBN: 978-3-642-53855-1.
  Detail

• 2012

  CHARVÁT, L.; SMRČKA, A.; VOJNAR, T. Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description. Proceedings of the 13th International Workshop on Microprocessor Test and Verification (MTV 2012). Austin, TX: Institute of Electrical and Electronics Engineers, 2012. p. 6-12. ISBN: 978-1-4673-4441-8.
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• 2010

  SMRČKA, A. Verification of Asynchronous and Parametrized Hardware Designs. Brno: Department of Intelligent Systems FIT BUT, 2010.
  Detail

  SMRČKA, A.; VOJNAR, T. Verification of Asynchronous and Parametrized Hardware Designs. FIT Monograph. FIT Monograph. Brno: Faculty of Information Technology BUT, 2010. 115 p. ISBN: 978-80-214-4214-6.
  Detail

  SMRČKA, A. Verification of Asynchronous and Parametrized Hardware Designs. Information Sciences and Technologies Bulletin of the ACM Slovakia, 2010, vol. 2, no. 2, p. 60-69. ISSN: 1338-1237.
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• 2008

  SMRČKA, A.; VOJNAR, T. Verifying Parametrised Hardware Designs Via Counter Automata. Hardware and Software, Verification and Testing. Lecture Notes in Computer Science. Lecture Notes in Computer Science. Heidelberg: Springer Verlag, 2008. p. 51-68. ISSN: 0302-9743.
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• 2007

  SMRČKA, A.; ŘEHÁK, V.; VOJNAR, T.; ŠAFRÁNEK, D.; MATOUŠEK, P.; ŘEHÁK, Z. Verifying VHDL Design with Multiple Clocks in SMV. In Formal Methods: Applications and Technology. Lecture Notes in Computer Science. Lecture Notes in Computer Science 4346. Bonn: Springer Verlag, 2007. p. 148-164. ISBN: 978-3-540-70951- 0. ISSN: 0302- 9743.
  Detail

• 2006

  SMRČKA, A.; HLÁVKA, P.; ŘEHÁK, V.; ŠAFRÁNEK, D.; ŠIMEČEK, P.; VOJNAR, T. Formal Verification of the CRC Algorithm Properties. In MEMICS 2006 Second Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Mikulov: 2006. p. 55-62. ISBN: 80-214-3287- X.
  Detail

  SMRČKA, A.; ŘEHÁK, V.; VOJNAR, T.; ŠAFRÁNEK, D.; MATOUŠEK, P.; ŘEHÁK, Z. Verifying VHDL Design with Multiple Clocks in SMV. Proceedings of FMICS 2006. Bonn: 2006. p. 140-155.
  Detail

  SMRČKA, A. High-level Modeling, Analysis and Verification of Programmable Hardware Design. Proceedings of the Junior Scientist Conference 2006. Vienna: TU Vienna, 2006. p. 93-94. ISBN: 3-902463-05- 8.
  Detail

• 2005

  MATOUŠEK, P., SMRČKA, A., VOJNAR, T. High-Level Modelling, Analysis, and Verification on FPGA- Based Hardware Design. In Correct Hardware Design and Verification Methods. Lecture Notes in Computer Science. Lecture Notes in Computer Science 3725/ 2005. Berlin: Springer Verlag, 2005. p. 371-375. ISBN: 978-3-540-29105- 3. ISSN: 0302- 9743.
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  SMRČKA, A. Abstract Model Verification of the Lookup Processor. In Proceedings of MOSIS' 05. Ostrava: 2005. p. 138-145. ISBN: 80-86840-10- 7.
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  SMRČKA, A. Towards Hardware Verification. In Proceedings of the 11th Conference Student EEICT 2005. Volume 3. Brno: Faculty of Information Technology BUT, 2005. p. 668-672. ISBN: 978-80-214-2890- 4.
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  SMRČKA, A., MATOUŠEK, P., VOJNAR, T. High-level Modelling, Analysis and Verification on FPGA- based Hardware Design. Brno: CESNET National Research and Education Network, 2005.
  Detail | WWW

• 2003

  SMRČKA, A. Universal disassembler. Proceedings of the International Conference and Competition - Student EEICT 2003. Brno: Faculty of Electrical Engineering and Communication BUT, 2003. p. 346-348. ISBN: 80-214-2401-X.
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*) Publications are generated once a 24 hours.