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Project detail
Duration: 01.03.2017 — 29.02.2020
Funding resources
Brno University of Technology - Vnitřní projekty VUT
- whole funder (2017-01-01 - 2018-12-31)
On the project
Hledání a ověřování nových algoritmů a výpočetních platforem uplatnitelných při návrhu, optimalizaci a realizaci moderních počítačových systémů. Budeme se zabývat zejména takovými systémy, které jsou založeny na rekonfigurovatelných nebo víceprocesorových architekturách, mají charakter vestavěných systémů, jsou vyžadovány vyšší stupeň spolehlivosti a jejich pokročilá optimalizace dle různých kritérií. Důraz je kladen na zintenzivnění podílu doktorandů na výsledcích a prezentaci výsledků na mezinárodní úrovni.
Mark
FIT-S-17-3994
Default language
Czech
People responsible
Bartoš Václav, Ing., Ph.D. - fellow researcherBidlo Michal, doc. Ing., Ph.D. - fellow researcherBudiský Jakub, Ing. - fellow researcherCrha Adam, Ing., Ph.D. - fellow researcherČekan Ondřej, Ing., Ph.D. - fellow researcherDobai Roland, Ing., Ph.D. - fellow researcherFučík Otto, doc. Dr. Ing. - fellow researcherFukač Tomáš, Ing., Ph.D. - fellow researcherGrochol David, Ing., Ph.D. - fellow researcherHrbáček Radek, Ing., Ph.D. - fellow researcherHusa Jakub, Ing., Ph.D. - fellow researcherHyrš Martin, Ing., Ph.D. - fellow researcherJaroš Jiří, doc. Ing., Ph.D. - fellow researcherJaroš Marta, Ing., Ph.D. - fellow researcherKekely Lukáš, Ing., Ph.D. - fellow researcherKekely Michal, Ing., Ph.D. - fellow researcherKešner Filip, Ing. - fellow researcherKidoň Marek, Ing. - fellow researcherKořenek Jan, doc. Ing., Ph.D. - fellow researcherKrčma Martin, Ing., Ph.D. - fellow researcherKrobot Pavel, Ing. - fellow researcherKučera Jan, Ing., Ph.D. - fellow researcherLojda Jakub, Ing., Ph.D. - fellow researcherMartínek Tomáš, doc. Ing., Ph.D. - fellow researcherMatoušek Denis, Ing. - fellow researcherMatoušek Jiří, Ing., Ph.D. - fellow researcherMrázek Vojtěch, Ing., Ph.D. - fellow researcherNevoral Jan, Ing., Ph.D. - fellow researcherNikl Vojtěch, Ing. - fellow researcherPánek Richard, Ing., Ph.D. - fellow researcherPodivínský Jakub, Ing., Ph.D. - fellow researcherRiša Michal, Ing. - fellow researcherRůžička Richard, doc. Ing., Ph.D., MBA - fellow researcherStrnadel Josef, Ing., Ph.D. - fellow researcherSzurman Karel, Ing., Ph.D. - fellow researcherŠimek Václav, Ing. - fellow researcherVašíček Zdeněk, doc. Ing., Ph.D. - fellow researcherVaverka Filip, Ing., Ph.D. - fellow researcherViktorin Jan, Ing. - fellow researcherVrána Roman, Ing. - fellow researcherWiglasz Michal, Ing. - fellow researcherWrona Jan, Ing. - fellow researcherZachariášová Marcela, Ing., Ph.D. - fellow researcherSekanina Lukáš, prof. Ing., Ph.D. - principal person responsible
Units
Department of Computer Systems- internal (2017-01-01 - 2019-12-31)Faculty of Information Technology- beneficiary (2017-01-01 - 2019-12-31)
Results
PODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; ZACHARIÁŠOVÁ, M.; KRČMA, M.; KOTÁSEK, Z. Functional Verification Based Platform for Evaluating Fault Tolerance Properties. Microprocessors and Microsystems, 2017, vol. 52, no. 5, p. 145-159. ISSN: 0141-9331.Detail
KIDOŇ, M.; DOBAI, R. Evolutionary design of hash functions for IP address hashing using genetic programming. In 2017 IEEE Congress on Evolutionary Computation (CEC). San Sebastian: Institute of Electrical and Electronics Engineers, 2017. p. 1720-1727. ISBN: 978-1-5090-4601-0.Detail
KEŠNER, F.; SEKANINA, L.; BRÁZDIL, M. Modular Framework for Detection of Inter-ictal Spikes in iEEG. In The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC'17). Los Alamos: Institute of Electrical and Electronics Engineers, 2017. p. 418-421. ISBN: 978-1-5090-2809-2.Detail
STRNADEL, J. On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. In Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2017. p. 352-355. ISBN: 978-1-5386-2146-2.Detail
PODIVÍNSKÝ, J.; LOJDA, J.; ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. Reliability Analysis and Improvement of FPGA-based Robot Controller. In Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Vídeň: IEEE Computer Society, 2017. p. 337-344. ISBN: 978-1-5386-2145-5.Detail
ČEKAN, O.; KOTÁSEK, Z. A Probabilistic Context-Free Grammar Based Random Test Program Generation. In Proceedings of 20th Euromicro Conference on Digital System Design. Vídeň: Technical University Wien, 2017. p. 356-359. ISBN: 978-1-5386-2145-5.Detail
WIGLASZ, M.; SEKANINA, L. Evolutionary Approximation of Gradient Orientation Module in HOG-based Human Detection System. In 2017 IEEE Global Conference on Signal and Information Processing GlobalSIP 2017. Montreal: IEEE Signal Processing Society, 2017. p. 1300-1304. ISBN: 978-1-5090-5989-8.Detail
LOJDA, J.; KOTÁSEK, Z. A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017. p. 79-80. ISBN: 978-80-01-06178-7.Detail
PODIVÍNSKÝ, J.; KOTÁSEK, Z. The Use of Functional Verification for Monitoring Impact of Faults in SRAM-based FPGAs. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017. p. 81-82. ISBN: 978-80-01-06178-7.Detail
SHAFIQUE, M.; HAFIZ, R.; JAVED, M.; ABBAS, S.; SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In 2017 IEEE Computer Society Annual Symposium on VLSI. Los Alamitos: IEEE Computer Society Press, 2017. p. 627-632. ISBN: 978-1-5090-6762-6.Detail
JAROŠ, M. Framework for Planning, Running and Monitoring Cooperating Computations. Počítačové architektúry & diagnostika PAD 2017. Bratislava: Slovak University of Technology in Bratislava, 2017. p. 20-23. ISBN: 978-80-972784-0-3.Detail
LOJDA, J.; KOTÁSEK, Z. Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy. Počítačové architektury & diagnostika 2017. Smolenice: Slovenská technická univerzita v Bratislavě, 2017. s. 59-62. ISBN: 978-80-972784-0-3.Detail
PÁNEK, R. Systémy odolné proti poruchám - metodika návrhu řadiče rekonfigurace. Počítačové architektury & diagnostika 2017. Smolenice: Slovenská technická univerzita v Bratislavě, 2017. s. 24-27. ISBN: 978-80-972784-0-3.Detail
SZURMAN, K.; KOTÁSEK, Z. State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture. Počítačové architektúry & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017. p. 51-54. ISBN: 978-80-972784-0-3.Detail
LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.; KRČMA, M. Data Types and Operations Modifications: a Practical Approach to Fault Tolerance in HLS. In Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017. p. 273-278. ISBN: 978-1-5386-3299-4.Detail
LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation. In Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017. p. 359-364. ISBN: 978-1-5386-3299-4.Detail
KEKELY, M.; KOŘENEK, J. Packet Classification with Limited Memory Resources. In In proceedings 2017 Euromicro Conference on Digital System Design. Vieden: Institute of Electrical and Electronics Engineers, 2017. p. 179-183. ISBN: 978-1-5386-2145-5.Detail
KEKELY, M.; KOŘENEK, J. Mapping of P4 Match Action Tables to FPGA. In Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017. p. 1-2. ISBN: 978-90-90-30428-1.Detail
KRČMA, M.; KOTÁSEK, Z. Approximation accuracy of different FPNN types. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017. p. 81-82. ISBN: 978-80-01-06178-7.Detail
KRČMA, M.; LOJDA, J.; KOTÁSEK, Z. Triple Modular Redundancy Used in Field Programmable Neural Networks. In Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017. p. 1-6. ISBN: 978-1-5386-3299-4.Detail
STRNADEL, J. Predictability Analysis of Interruptible Systems by Statistical Model Checking. IEEE Design and Test, 2018, vol. 35, no. 2, p. 57-63. ISSN: 2168-2356.Detail
VYSOCKÝ, O.; BESEDA, M.; ŘÍHA, L.; ZAPLETAL, J.; NIKL, V.; LYSAGHT, M.; KANNAN, V. Evaluation of the HPC Applications Dynamic Behavior in Terms of Energy Consumption. In PROCEEDINGS OF THE FIFTH INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, GRID AND CLOUD COMPUTING FOR ENGINEERING. Civil-Comp Proceedings. Stirlingshire: Civil-Comp Press, 2017. p. 30-49. ISBN: 978-1-905088-66-9.Detail
LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.; KRČMA, M. Majority Type and Redundancy Level Influences on Redundant Data Types Approach for HLS. In 2018 16th Biennial Baltic Electronics Conference (BEC). Tallinn: IEEE Computer Society, 2018. p. 1-4. ISBN: 978-1-5386-7312-6.Detail
MRÁZEK, V.; VAŠÍČEK, Z. Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria. In Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18). Kyoto: Association for Computing Machinery, 2018. p. 294-295. ISBN: 978-1-4503-5764-7.Detail
NEVORAL, J.; RŮŽIČKA, R.; ŠIMEK, V. CMOS Gates with Second Function. In 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). Hong Kong: IEEE Computer Society, 2018. p. 82-87. ISBN: 978-1-5386-7099-6.Detail
LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018. p. 80-86. ISBN: 978-1-5386-5710-2.Detail
STRNADEL, J. Statistical Model Checking of Processor Systems in Various Interrupt Scenarios. In Proceedings of 8th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA). Lecture Notes in Computer Science. Lecture Notes in Computer Science, Vol. 11245. Cham: Springer International Publishing, 2018. p. 414-429. ISSN: 0302-9743.Detail
NIKL, V.; ŘÍHA, L.; VYSOCKÝ, O.; ZAPLETAL, J. Optimal Hardware Parameters Prediction for Best Energy-to-Solution of Sparse Matrix Operations Using Machine Learning Techniques. INFOCOMP 2018. The Eighth International Conference on Advanced Communications and Computation. Barcelona: International Academy, Research, and Industry Association, 2018. p. 43-48. ISBN: 978-1-61208-655-2.Detail
PODIVÍNSKÝ, J.; LOJDA, J.; ČEKAN, O.; KOTÁSEK, Z. Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018. p. 229-236. ISBN: 978-1-5386-7376-8.Detail
LOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation. In Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018. p. 244-251. ISBN: 978-1-5386-7376-8.Detail
NEVORAL, J.; RŮŽIČKA, R.; ŠIMEK, V. From Ambipolarity to Multifunctionality: Novel Library of Polymorphic Gates Using Double-Gate FETs. In 2018 21st Euromicro Conference on Digital System Design. Praha: Institute of Electrical and Electronics Engineers, 2018. p. 657-664. ISBN: 978-1-5386-7376-8.Detail
ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Program Generation Through a Probabilistic Constrained Grammar. In Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. Praha: IEEE Computer Society, 2018. p. 214-220. ISBN: 978-1-5386-7376-8.Detail
MATOUŠEK, D.; KUBIŠ, J.; MATOUŠEK, J.; KOŘENEK, J. Regular Expression Matching with Pipelined Delayed Input DFAs for High-speed Networks. In ANCS 2018 - Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018. p. 104-110. ISBN: 978-1-4503-5902-3.Detail
SUMBALOVÁ, L.; ŠTOURAČ, J.; MARTÍNEK, T.; BEDNÁŘ, D.; DAMBORSKÝ, J. HotSpot Wizard 3.0: Web Server for Automated Design of Mutations and Smart Libraries based on Sequence Input Information. Nucleic Acids Research, 2018, vol. 46, no. 1, p. 356-362. ISSN: 1362-4962.Detail
FIŠER, P.; ŠIMEK, V. Optimum Polymorphic Circuits Synthesis Method. In 13th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Taormina: IEEE Circuits and Systems Society, 2018. p. 1-6. ISBN: 978-1-5386-5290-9.Detail
CRHA, A.; ŠIMEK, V.; RŮŽIČKA, R. Towards novel format for representation of polymorphic circuits. In 13th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Taormina: IEEE Circuits and Systems Society, 2018. p. 1-2. ISBN: 978-1-5386-5290-9.Detail
LOJDA, J.; KOTÁSEK, Z. Fault Tolerance in HLS for the Purposes of Reliable System Design Automation. Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2018. p. 31-32. ISBN: 978-80-01-06456-6.Detail
PODIVÍNSKÝ, J.; LOJDA, J.; KOTÁSEK, Z. An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018. p. 63-69. ISBN: 978-1-5386-5710-2.Detail
PODIVÍNSKÝ, J.; KOTÁSEK, Z. Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2018. p. 33-34. ISBN: 978-80-01-06456-6.Detail
PÁNEK, R.; LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. In Proceedings of IEEE East-West Design & Test Symposium. Kazaň: IEEE Computer Society, 2018. p. 129-134. ISBN: 978-1-5386-5710-2.Detail
LOJDA, J.; KOTÁSEK, Z. Automatizace návrhu spolehlivých systémů a její dílčí komponenty. Počítačové architektury & diagnostika 2018. Stachy: Západočeská univerzita v Plzni, 2018. s. 5-8. ISBN: 978-80-261-0814-6.Detail
JAROŠ, M. Scientific Workflows Management. Počítačové architektúry & diagnostika PAD 2018. Plzeň: University of West Bohemia in Pilsen, 2018. p. 25-28. ISBN: 978-80-261-0814-6.Detail
PÁNEK, R. Metodika návrhu řadiče rekonfigurace pro Systémy odolné proti poruchám. Počítačové architektury & diagnostika 2018. Stachy: Západočeská univerzita v Plzni, 2018. s. 21-24. ISBN: 978-80-261-0814-6.Detail
NEVORAL, J.; RŮŽIČKA, R. Efficient Implementation of Bi-functional RTL Components - Case Study. In 2018 New Generation of CAS (NGCAS). Valletta: IEEE Circuits and Systems Society, 2018. p. 25-28. ISBN: 978-1-5386-7680-6.Detail
ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. Input and Output Generation for the Verification of ALU: a Use Case. In Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018. Kazan: IEEE Computer Society, 2018. p. 331-336. ISBN: 978-1-5386-5710-2.Detail
CASTELLI, M.; SEKANINA, L.; ZHANG, M.; CAGNONI, S.; GARCÍA-SÁNCHEZ, P. 21st European Conference on Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2018. p. 0-0. ISBN: 978-3-319-77552-4.Detail
TREFZER, M.; SEKANINA, L. Guest Editorial: Bio-inspired Hardware and Evolvable Systems. IET Computers and Digital Techniques. 2018. p. 121-121. ISSN: 1751-8601.Detail
PODIVÍNSKÝ, J.; LOJDA, J.; KOTÁSEK, Z. Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019. p. 97-100. ISBN: 978-1-7281-1756-0.Detail
LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019. p. 93-96. ISBN: 978-1-7281-1756-0.Detail
STRNADEL, J. Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates. In Design, Automation & Test in Europe Conference & Exhibition (DATE). Florence: IEEE Computer Society, 2019. p. 614-617. ISBN: 978-3-9819263-2-3.Detail
KOCNOVÁ, J.; VAŠÍČEK, Z. Towards a Scalable EA-based Optimization of Digital Circuits. In Genetic Programming 22nd European Conference, EuroGP 2019. Cham: Springer International Publishing, 2019. p. 81-97. ISBN: 978-3-030-16669-4.Detail
SZURMAN, K.; KOTÁSEK, Z. Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019. p. 32-35. ISBN: 978-1-7281-1756-0.Detail
SZURMAN, K.; KOTÁSEK, Z. Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430. In 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019). Cluj-Napoca: IEEE Computer Society, 2019. p. 136-140. ISBN: 978-1-7281-0073-9.Detail
SEKANINA, L.; HU, T.; LOURENÇO, N.; RICHTER, H.; GARCÍA-SÁNCHEZ, P. Genetic Programming 22nd European Conference. Lecture Notes in Computer Science. Cham: Springer International Publishing, 2019. p. 0-0. ISBN: 978-3-030-16669-4.Detail
TREEBY, B.; JAROŠ, J.; MARTIN, E.; COX, B. From Biology to Bytes: Predicting the Path of Ultrasound Waves Through the Human Body. Acoustics Today, 2019, vol. 15, no. 2, p. 36-44. ISSN: 1557-0223.Detail
VRÁNA, R.; KOŘENEK, J.; NOVÁK, D. Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic. In Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Cluj-Napoca: Institute of Electrical and Electronics Engineers, 2019. p. 1-6. ISBN: 978-1-7281-0073-9.Detail
FUKAČ, T.; KOŘENEK, J. Hash-based Pattern Matching for High Speed Networks. In Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Cluj-Napoca: Institute of Electrical and Electronics Engineers, 2019. p. 1-5. ISBN: 978-1-7281-0073-9.Detail
KOCNOVÁ, J.; VAŠÍČEK, Z. Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits. In GECCO '19 Proceedings of the Genetic and Evolutionary Computation Conference Companion. New York: Association for Computing Machinery, 2019. p. 377-378. ISBN: 978-1-4503-6748-6.Detail
KRČMA, M.; KOTÁSEK, Z.; LOJDA, J. Detecting hard synapses faults in artificial neural networks. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago de Chile: IEEE Computer Society, 2019. p. 1-6. ISBN: 978-1-7281-1756-0.Detail
NEVORAL, J.; ŠIMEK, V.; RŮŽIČKA, R. PoLibSi: Path Towards Intrinsically Reconfigurable Components. In 2019 22nd Euromicro Conference on Digital System Design (DSD). Kallithea, Chalkidiki: Institute of Electrical and Electronics Engineers, 2019. p. 328-334. ISBN: 978-1-7281-2861-0.Detail
CRHA, A.; ŠIMEK, V.; RŮŽIČKA, R. PAIG Rewriting: The Way to Scalable Multifunctional Digital Circuits Synthesis. In 22nd Euromicro Conference on Digital System Design. Kallithea, Chalkidiki: Institute of Electrical and Electronics Engineers, 2019. p. 335-342. ISBN: 978-1-7281-2861-0.Detail
ČEKAN, O.; PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. In Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019. p. 506-513. ISBN: 978-1-7281-2861-0.Detail
HYRŠ, M.; SCHWARZ, J. An Analysis of Control Parameters of Copula-based EDA Algorithm with Model Migration. In GECCO '19 Proceedings of the Genetic and Evolutionary Computation Conference Companion. Praha: Association for Computing Machinery, 2019. p. 259-260. ISBN: 978-1-4503-6748-6.Detail
MATOUŠEK, J. Addressing Issues in Research on Packet Classification in Core Networks. Brno: Faculty of Information Technology BUT, 2019. p. 0-0.Detail
JAROŠ, M. Adaptive Execution Planning in Workflow Management Systems. Počítačové architektury a diagnostika 2019. Doksy: Academic and Medical Conference Agency, 2019. p. 23-26. ISBN: 978-80-88214-20-5.Detail
VAVERKA, F. Towards Large-scale Ultrasound Simulations in Soft Tissue for Medical Applications. PAD 2019. Doksy: Academic and Medical Conference Agency, 2019. p. 64-67. ISBN: 978-80-88214-20-5.Detail
KUKLIŠ, F. Optimization of Evolutionary Strategy using Island Model to Design HIFU Treatment Plans. Sborník semináře PAD 2019. Doksy: Academic and Medical Conference Agency, 2019. p. 5-8. ISBN: 978-80-88214-20-5.Detail
ČEKAN, O.; PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Smart Electronic Locks and Their Reliability. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2019. p. 4-5. ISBN: 978-80-01-06607-2.Detail
MICENKOVÁ, L.; BOSÁK, J.; SMATANA, S.; NOVOTNÝ, A.; BUDINSKÁ, E.; ŠMAJS, D. Administration of the Probiotic Escherichia coli Strain A0 34/86 Resulted in a Stable Colonization of the Human Intestine During the First Year of Life. Probiotics and Antimicrobial Proteins, 2020, vol. 12, no. 2, p. 343-350. ISSN: 1867-1314.Detail
STAMENKOVIC, Z.; BOSIO, A.; CSEREY, G.; NOVÁK, O.; PLESKACZ, W.; SEKANINA, L.; STEININGER, A.; STOJANOVIC, G.; STOPJAKOVÁ, V. International Symposium on Design and Diagnostics of Electronic Circuits and Systems. In 2019 IEEE International Test Conference. Washington, DC: Institute of Electrical and Electronics Engineers, 2019. p. 1-4. ISBN: 978-1-7281-4823-6.Detail
MATOUŠEK, D.; MATOUŠEK, J.; KOŘENEK, J. High-speed Regular Expression Matching with Pipelined Memory-based Automata. Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018. Boulder, CO: IEEE Computer Society, 2018. p. 214-214. ISBN: 978-1-5386-5522-1.Detail
FIŠER, P.; HÁLEČEK, I.; SCHMIDT, J.; ŠIMEK, V. SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2019, vol. 28, no. 1, p. 1-29. ISSN: 1793-6454.Detail
SZURMAN, K.; KOTÁSEK, Z. Fault Recovery for Coarse-Grained TMR Soft-Core Processor Using Partial Reconfiguration and State Synchronization. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2019. p. 6-7. ISBN: 978-80-01-06607-2.Detail
PODIVÍNSKÝ, J.; LOJDA, J.; KOTÁSEK, Z. FPGA-based Robot Controller: An Experimental Evaluation of Fault Tolerance Properties. INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť: 2018. p. 9-12.Detail
ČEKAN, O.; KOTÁSEK, Z. Random Test Generation Through a Probabilistic Constrained Grammar. INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť: 2018. p. 5-8.Detail