Publikace

• 2023

  KEKELY, M.; KOŘENEK, J. Optimizing Packet Classification on FPGA. In PROCEEDINGS 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Tallinn: Institute of Electrical and Electronics Engineers, 2023. s. 7-12. ISBN: 979-8-3503-3277-3. ISSN: 2334-3133.
  Detail | WWW

• 2020

  KEKELY, M.; KEKELY, L.; KOŘENEK, J. General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocessors and Microsystems, 2020, roč. 73, č. 3, s. 1-12. ISSN: 0141-9331.
  Detail | WWW

  KEKELY, M.; HYNEK, K.; ČEJKA, T. Pipelined ALU for effective external memory access in FPGA. In 2020 23RD EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2020). Kranj: Institute of Electrical and Electronics Engineers, 2020. s. 97-100. ISBN: 978-1-7281-9535-3.
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• 2018

  CABAL, J.; BENÁČEK, P.; KEKELY, L.; KEKELY, M.; PUŠ, V.; KOŘENEK, J. Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York: Association for Computing Machinery, 2018. s. 249-258. ISBN: 978-1-4503-5614-5.
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  MARTINÁSEK, Z.; HAJNÝ, J.; SMÉKAL, D.; MALINA, L.; MATOUŠEK, D.; KEKELY, M.; MENTENS, N. 200 Gbps Hardware Accelerated Encryption System for FPGA Network Cards. In The Second Workshop on Attacks and Solutions in Hardware Security (ASHES’18). Toronto, Canada: ACM, 2018. s. 11-17. ISBN: 978-1-4503-5996-2.
  Detail | WWW

  KEKELY, M.; KEKELY, L.; KOŘENEK, J. Memory Aware Packet Matching Architecture for High-Speed Networks. In Proceedings of the 21st Euromicro Conference on Digital Systems Design. Praha: IEEE Computer Society, 2018. s. 1-8. ISBN: 978-1-5386-7376-8.
  Detail | WWW

• 2017

  KEKELY, M.; KOŘENEK, J. Mapping of P4 Match Action Tables to FPGA. In Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017. s. 1-2. ISBN: 978-90-90-30428-1.
  Detail

  KEKELY, M.; KOŘENEK, J. Packet Classification with Limited Memory Resources. In In proceedings 2017 Euromicro Conference on Digital System Design. Vieden: Institute of Electrical and Electronics Engineers, 2017. s. 179-183. ISBN: 978-1-5386-2145-5.
  Detail

*) Citace publikací se generují jednou za 24 hodin.