Publikace

• 2023

  KEKELY, M.; KOŘENEK, J. Optimizing Packet Classification on FPGA. In PROCEEDINGS 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Tallinn: Institute of Electrical and Electronics Engineers, 2023. s. 7-12. ISBN: 979-8-3503-3277-3. ISSN: 2334-3133.
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  KOŠAŘ, V.; ŠIŠMIŠ, L.; MATOUŠEK, J.; KOŘENEK, J. Accelerating IDS Using TLS Pre-Filter in FPGA. In Proceedings - IEEE Symposium on Computers and Communications. Tunis: IEEE Computer Society, 2023. s. 436-442. ISBN: 979-8-3503-0048-2.
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  ŠIŠMIŠ, L.; KOŘENEK, J. Analysis of TLS Prefiltering for IDS Acceleration. In Passive and Active Measurement 2023. Lecture Notes in Computer Science. Lecture Notes in Computer Science. Madrid: Springer Nature Switzerland AG, 2023. s. 85-109. ISBN: 978-3-031-28485-4. ISSN: 0302-9743.
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• 2022

  ŠIŠMIŠ, L.; KOŘENEK, J. Accelerating Suricata with DPDK Prefilters: 386 Days Later. Atény: 2022. s. 0-0.
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  MATOUŠEK, J.; LUČANSKÝ, A.; JANEČEK, D.; SABO, J.; KOŘENEK, J.; ANTICHI, G. ClassBench-ng: Benchmarking Packet Classification Algorithms in the OpenFlow Era. IEEE-ACM TRANSACTIONS ON NETWORKING, 2022, roč. 30, č. 5, s. 1912-1925. ISSN: 1558-2566.
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  ŠIŠMIŠ, L.; KOŘENEK, J. Accelerating Suricata with DPDK. Arcachon: 2022. s. 0-0.
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• 2021

  KOŘENEK, J.; VRÁNA, R. Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis. In Proceedings - 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2021. IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Vídeň: Institute of Electrical and Electronics Engineers, 2021. s. 115-118. ISBN: 978-1-6654-3595-6.
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  FUKAČ, T.; KOŘENEK, J.; MATOUŠEK, J. Scalability of Hash-based Pattern Matching for High-speed Network Security and Monitoring. In Proceedings - IEEE Symposium on Computers and Communications. Athens: Institute of Electrical and Electronics Engineers, 2021. s. 1-6. ISBN: 978-1-6654-2744-9.
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  FUKAČ, T.; MATOUŠEK, J.; KOŘENEK, J.; KEKELY, L. Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks. In 2021 International Conference on Field-Programmable Technology, ICFPT 2021. Auckland: Institute of Electrical and Electronics Engineers, 2021. s. 185-193. ISBN: 978-1-6654-2010-5.
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• 2020

  KEKELY, M.; KEKELY, L.; KOŘENEK, J. General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocessors and Microsystems, 2020, roč. 73, č. 3, s. 1-12. ISSN: 0141-9331.
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  KEKELY, L.; CABAL, J.; PUŠ, V.; KOŘENEK, J. Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. In Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Kranj: IEEE Computer Society, 2020. s. 49-56. ISBN: 978-1-7281-9535-3.
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  KOŘENEK, J.; KORČEK, P.; KEKELY, L. Akcelerace analýzy síťového provozu. DSM Data Security Management, 2020, roč. 24, č. 4, s. 30-34. ISSN: 1211-8737.
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  FUKAČ, T.; KOŠAŘ, V.; KOŘENEK, J.; MATOUŠEK, J. Increasing Throughput of Intrusion Detection Systems by Hash-Based Short String Pre-Filter. In Proceedings - Conference on Local Computer Networks, LCN. Sydney (virtual): Institute of Electrical and Electronics Engineers, 2020. s. 509-514. ISBN: 978-1-7281-7158-6.
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  KUČERA, J.; POPESCU, D.; WANG, H.; MOORE, A.; KOŘENEK, J.; ANTICHI, G. Enabling Event-Triggered Data Plane Monitoring. In SOSR 2020 - Proceedings of the 2020 Symposium on SDN Research. New York, NY: Association for Computing Machinery, 2020. s. 14-26. ISBN: 978-1-4503-7101-8.
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• 2019

  KUČERA, J.; KEKELY, L.; PIECEK, A.; KOŘENEK, J. General IDS Acceleration for High-Speed Networks. In Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Orlando: Institute of Electrical and Electronics Engineers, 2019. s. 366-373. ISBN: 978-1-5386-8477-1.
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  HAVLENA, V.; ČEŠKA, M.; HOLÍK, L.; KOŘENEK, J.; LENGÁL, O.; MATOUŠEK, D.; MATOUŠEK, J.; SEMRIČ, J.; VOJNAR, T. Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata. In Proceedings - 27th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019. San Diego, CA: Institute of Electrical and Electronics Engineers, 2019. s. 109-117. ISBN: 978-1-7281-1131-5.
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  KEKELY, L.; CABAL, J.; KOŘENEK, J. Effective FPGA Architecture for General CRC. In Architecture of Computing Systems - ARCS 2019. Neuvedeno: Springer International Publishing, 2019. s. 211-223. ISBN: 978-3-030-18655-5.
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  VRÁNA, R.; KOŘENEK, J.; NOVÁK, D. Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic. In Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Cluj-Napoca: Institute of Electrical and Electronics Engineers, 2019. s. 1-6. ISBN: 978-1-7281-0073-9.
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  FUKAČ, T.; KOŘENEK, J. Hash-based Pattern Matching for High Speed Networks. In Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Cluj-Napoca: Institute of Electrical and Electronics Engineers, 2019. s. 1-5. ISBN: 978-1-7281-0073-9.
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• 2018

  KUČERA, J.; POPESCU, D.; ANTICHI, G.; MOORE, A.; KOŘENEK, J. Elastic Trie: Enabling Event Triggered Monitoring in the Dataplane. SIGCOMM '18 Proceedings of the 2018 ACM SIGCOMM Conference. Budapest: Association for Computing Machinery, 2018. s. 1-12.
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  MATOUŠEK, D.; MATOUŠEK, J.; KOŘENEK, J. High-speed Regular Expression Matching with Pipelined Memory-based Automata. Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018. Boulder, CO: IEEE Computer Society, 2018. s. 214-214. ISBN: 978-1-5386-5522-1.
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  CABAL, J.; BENÁČEK, P.; KEKELY, L.; KEKELY, M.; PUŠ, V.; KOŘENEK, J. Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York: Association for Computing Machinery, 2018. s. 249-258. ISBN: 978-1-4503-5614-5.
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  KOŘENEK, J. Hardware Acceleration in Computer Networks. Brno: 2018. s. 0-0.
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  KEKELY, L.; CABAL, J.; KOŘENEK, J. High-Speed Computation of CRC Codes for FPGAs. In Proceedings of the 2018 International Conference on Field-Programmable Technology (FPT 2018). Naha: IEEE Computer Society, 2018. s. 237-240. ISBN: 978-1-7281-0214-6.
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  KEKELY, M.; KEKELY, L.; KOŘENEK, J. Memory Aware Packet Matching Architecture for High-Speed Networks. In Proceedings of the 21st Euromicro Conference on Digital Systems Design. Praha: IEEE Computer Society, 2018. s. 1-8. ISBN: 978-1-5386-7376-8.
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  KUČERA, J.; KEKELY, L.; PUŠ, V.; PIECEK, A.; KOŘENEK, J. Hardware Acceleration of Intrusion Detection Systems for High-Speed Networks. In Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018. s. 177-178. ISBN: 978-1-4503-5902-3.
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  MATOUŠEK, D.; KUBIŠ, J.; MATOUŠEK, J.; KOŘENEK, J. Regular Expression Matching with Pipelined Delayed Input DFAs for High-speed Networks. In ANCS 2018 - Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018. s. 104-110. ISBN: 978-1-4503-5902-3.
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• 2017

  MATOUŠEK, J.; ANTICHI, G.; LUČANSKÝ, A.; MOORE, A.; KOŘENEK, J. ClassBench-ng: Recasting ClassBench After a Decade of Network Evolution. In Proceedings - 2017 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2017. Beijing: IEEE Computer Society, 2017. s. 204-216. ISBN: 978-1-5090-6386-4.
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  KEKELY, M.; KOŘENEK, J. Packet Classification with Limited Memory Resources. In In proceedings 2017 Euromicro Conference on Digital System Design. Vieden: Institute of Electrical and Electronics Engineers, 2017. s. 179-183. ISBN: 978-1-5386-2145-5.
  Detail

  KEKELY, M.; KOŘENEK, J. Mapping of P4 Match Action Tables to FPGA. In Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017. s. 1-2. ISBN: 978-90-90-30428-1.
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  DOBAI, R.; KOŘENEK, J.; SEKANINA, L. Evolutionary design of hash function pairs for network filters. APPLIED SOFT COMPUTING, 2017, roč. 56, č. 7, s. 173-181. ISSN: 1568-4946.
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• 2016

  DOBAI, R.; KOŘENEK, J.; SEKANINA, L. Adaptive Development of Hash Functions in FPGA-Based Network Routers. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: IEEE Computational Intelligence Society, 2016. s. 1-8. ISBN: 978-1-5090-4240-1.
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  KOŘENEK, J.; VIKTORIN, J. Packet Processing on FPGA SoC with DPDK. In 26th International Conference on Field-Programmable Logic and Applications. Lausanne: École Polytechnique Fédérale de Lausanne, 2016. s. 578-579. ISBN: 978-2-8399-1844-2.
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  GROCHOL, D.; SEKANINA, L.; KOŘENEK, J.; ŽÁDNÍK, M.; KOŠAŘ, V. Evolutionary Circuit Design for Fast FPGA-Based Classification of Network Application Protocols. APPLIED SOFT COMPUTING, 2016, roč. 38, č. 1, s. 933-941. ISSN: 1568-4946.
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  MATOUŠEK, D.; KOŘENEK, J.; PUŠ, V. High-speed Regular Expression Matching with Pipelined Automata. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. s. 93-100. ISBN: 978-1-5090-5602-6.
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  BARTOŠ, V.; KOŘENEK, J. Evaluating Reputation of Internet Entities. In Management and Security in the Age of Hyperconnectivity. Lecture Notes in Computer Science. Munich: Springer International Publishing, 2016. s. 132-136. ISBN: 978-3-319-39813-6.
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  KOŠAŘ, V.; KOŘENEK, J. Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA. In Proceedings of The 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016. s. 591-598. ISBN: 978-1-5090-2816-0.
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• 2015

  DOBAI, R.; KOŘENEK, J. Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications. In 2015 IEEE Symposium Series on Computational Intelligence. Cape Town: Institute of Electrical and Electronics Engineers, 2015. s. 1214-1219. ISBN: 978-1-4799-7560-0.
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  GROCHOL, D.; SEKANINA, L.; ŽÁDNÍK, M.; KOŘENEK, J. A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. In Applications of Evolutionary Computation, 18th European Conference. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. s. 67-78. ISBN: 978-3-319-16548-6.
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  KOŠAŘ, V.; KOŘENEK, J. Towards Efficient Field Programmeable Pattern Matching Array. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. s. 1-8. ISBN: 978-1-4673-8035-5.
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  KEKELY, L.; KUČERA, J.; PUŠ, V.; KOŘENEK, J.; VASILAKOS, A. Software Defined Monitoring of Application Protocols. IEEE TRANSACTIONS ON COMPUTERS, 2015, roč. 65, č. 2, s. 615-626. ISSN: 0018-9340.
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• 2014

  KOŠAŘ, V.; KOŘENEK, J. On NFA-Split Architecture Optimizations. In 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Warsaw: IEEE Computer Society, 2014. s. 274-277. ISBN: 978-1-4799-4558-0.
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  KEKELY, L.; ŽÁDNÍK, M.; MATOUŠEK, J.; KOŘENEK, J. Fast Lookup for Dynamic Packet Filtering in FPGA. In Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014. Warszawa: IEEE Computer Society, 2014. s. 219-222. ISBN: 978-1-4799-4558-0.
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  PUŠ, V.; KEKELY, L.; KOŘENEK, J. Design Methodology of Configurable High Performance Packet Parser for FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. s. 189-194. ISBN: 978-1-4799-4558-0.
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  DVOŘÁK, M.; KOŘENEK, J. Low Latency Book Handling in FPGA for High Frequency Trading. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. s. 175-178. ISBN: 978-1-4799-4558-0.
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  KEKELY, L.; PUŠ, V.; KOŘENEK, J. Software Defined Monitoring of Application Protocols. In Proceedings of IEEE INFOCOM 2014 - IEEE Conference on Computer Communications. Toronto: IEEE Computer Society, 2014. s. 1725-1733. ISBN: 978-1-4799-3360-0.
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  VIKTORIN, J.; KORČEK, P.; KOŘENEK, J.; FUKAČ, T. Network monitoring probe based on Xilinx Zynq. In Proceedings of the 2012 Tenth ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2014). Marina del Rey, CA, USA: Association for Computing Machinery, 2014. s. 237-238. ISBN: 978-1-4503-2839-5.
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  KOŠAŘ, V.; KOŘENEK, J. Multi-Stride NFA-Split Architecture for Regular Expression Matching Using FPGA. Proceedings of the 9th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: NOVPRESS s.r.o., 2014. s. 77-88. ISBN: 978-80-214-5022-6.
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  KEKELY, L.; PUŠ, V.; BENÁČEK, P.; KOŘENEK, J. Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring. In 2014 24th International Conference on Field Programmable Logic and Applications (FPL 2014). Munich: IEEE Circuits and Systems Society, 2014. s. 264-267. ISBN: 978-3-00-044645-0.
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  KOŘENEK, J.; KORČEK, P.; VIKTORIN, J. Jak propojit Linux s FPGA?. DPS Elektronika od A do Z. 2014. s. 24-25. ISSN: 1805-5044.
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• 2013

  KOŠAŘ, V.; ŽÁDNÍK, M.; KOŘENEK, J. NFA Reduction for Regular Expressions Matching Using FPGA. Proceedings of the 2013 International Conference on Field Programmable Technology. Kyoto: IEEE Computer Society, 2013. s. 338-341. ISBN: 978-1-4799-2199-7.
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  VIKTORIN, J.; KORČEK, P.; KOŠAŘ, V.; KOŘENEK, J. Framework for Fast Prototyping of Applications running on Reconfigurable Systems on Chip. Proceedings of the 2013 Conference on Design & Architectures for Signal & Image Processing. Cagliari: European Electronic Chips & Systems design Initiative, 2013. s. 355-356. ISBN: 979-10-92279-01-6.
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  MATOUŠEK, J.; SKAČAN, M.; KOŘENEK, J. Towards Hardware Architecture for Memory Efficient IPv4/IPv6 Lookup in 100 Gbps Networks. In Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013. Brno: IEEE Computer Society, 2013. s. 108-111. ISBN: 978-1-4673-6136-1.
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  KAŠTIL, J.; KOŠAŘ, V.; KOŘENEK, J. Hardware Architecture for the Fast Pattern Matching. 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Brno: IEEE Computer Society, 2013. s. 120-123. ISBN: 978-1-4673-6133-0.
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  MATOUŠEK, J.; SKAČAN, M.; KOŘENEK, J. Memory Efficient IP Lookup in 100 Gbps Networks. In 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings. Porto: IEEE Circuits and Systems Society, 2013. s. 1-8. ISBN: 978-1-4799-0004-6.
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• 2012

  PUŠ, V.; KOŘENEK, J. Reducing memory in high-speed packet classification. Proceedings of the 8th International Wireless Communications and Mobile Computing Conference. Limassol: Frederick University, 2012. s. 437-442. ISBN: 978-1-4577-1377-4.
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  KOŘENEK, J.; KORČEK, P.; KOŠAŘ, V.; ŽÁDNÍK, M.; VIKTORIN, J. A New Embedded Platform for Rapid Development of Networking Applications. Proceedings of the 2012 Seventh ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2012). Austin: IEEE Computer Society, 2012. s. 81-82. ISBN: 978-1-4503-1684-2.
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  KEKELY, L.; PUŠ, V.; KOŘENEK, J. Low-Latency Modular Packet Header Parser for FPGA. ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Austin: Association for Computing Machinery, 2012. s. 77-78. ISBN: 978-1-4503-1685-9.
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• 2011

  PUŠ, V.; TOBOLA, J.; KAŠTIL, J.; KOŠAŘ, V.; KOŘENEK, J. Netbench - the Framework for Evaluation of Packet Processing Algorithms. Proceedings of the 7th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. New York: IEEE Computer Society, 2011. s. 95-96. ISBN: 978-0-7695-4521-9.
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  KOŠAŘ, V.; KOŘENEK, J. Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. s. 401-402. ISBN: 978-1-4244-9753-9.
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  PUŠ, V.; KAJAN, M.; KOŘENEK, J. Hardware Architecture for Packet Classification with Prefix Coloring. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. s. 231-236. ISBN: 978-1-4244-9753-9.
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  TOBOLA, J.; KOŘENEK, J. Effective Hash-based IPv6 Longest Prefix Match. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. s. 325-328. ISBN: 978-1-4244-9753-9.
  Detail

• 2010

  KOŘENEK, J. Fast Regular Expression Matching Using FPGA. Information Sciences and Technologies Bulletin of the ACM Slovakia, 2010, roč. 2, č. 2, s. 103-111. ISSN: 1338-1237.
  Detail

  KOŘENEK, J.; KOŠAŘ, V. Efficient Mapping of Nondeterministic Automata to FPGA for Fast Regular Expression Matching. Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Vienna: IEEE Computer Society, 2010. s. 54-59. ISBN: 978-1-4244-6610-8.
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  KAŠTIL, J.; KOŘENEK, J. Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing. Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Vienna: IEEE Computer Society, 2010. s. 149-152. ISBN: 978-1-4244-6610-8.
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  KOŘENEK, J.; KOŠAŘ, V. Architektura NFA Split pro rychlé hledání regulárních výrazů. Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. La Jolla: Association for Computing Machinery, 2010. s. 1-2. ISBN: 978-1-4503-0379-8.
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  KAŠTIL, J.; KOŘENEK, J. High Speed Pattern Matching Algorithm Based on Deterministic Finite Automata with Faulty Transition Table. Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. La Jolla: Association for Computing Machinery, 2010. s. 1-2. ISBN: 978-1-4503-0379-8.
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  KAJAN, M.; KOŘENEK, J. Efficient packet classification algorithm based on entropy. Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. La Jolla: Association for Computing Machinery, 2010. s. 11-12. ISBN: 978-1-4503-0379-8.
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  KOŘENEK, J.; PUŠ, V. Memory Optimization for Packet Classification Algorithms in FPGA. Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vídeň: IEEE Computer Society, 2010. s. 297-300. ISBN: 978-1-4244-6610-8.
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• 2009

  KAŠTIL, J.; KOŘENEK, J.; LENGÁL, O. Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing. 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009. s. 823-289. ISBN: 978-0-7695-3782-5.
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  PUŠ, V.; KOŘENEK, J. Fast and scalable packet classification using perfect hash functions. Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays. Association for Computing Machinery. New York: Association for Computing Machinery, 2009. s. 229-236. ISBN: 978-1-60558-410-2.
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  KOŘENEK, J.; PUŠ, V. Memory Optimization for Packet Classification Algorithms. Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Association for Computing Machinery. New York: Association for Computing Machinery, 2009. s. 165-166. ISBN: 978-1-60558-630-4.
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  KOBIERSKÝ, P.; KOŘENEK, J.; POLČÁK, L. Packet Header Analysis and Field Extraction for Multigigabit Networks. Proceedings of the 2009 IEEE Symphosium on Design and Diagnostics of Electronic Circuits and Systems. Liberec: IEEE Computer Society, 2009. s. 96-101. ISBN: 978-1-4244-3339-1.
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• 2008

  ŽÁDNÍK, M.; KOŘENEK, J.; LENGÁL, O.; KOBIERSKÝ, P. Network Probe for Flexible Flow Monitoring. Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008. s. 213-218. ISBN: 978-1-4244-2276-0.
  Detail

  KAŠTIL, J.; KOŘENEK, J. Deterministic Finite Automaton with Perfect Hashing for Fast Pattern Matching. Proceedings of Junior Scientist Conference 2008. Vienna: Technical University Wien, 2008. s. 103-104. ISBN: 978-3-200-01612-5.
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  MÁLEK, T.; MARTÍNEK, T.; KOŘENEK, J. GICS: Generic Interconnection System. 2008 International Conference on Field Programmable Logic and Applications. Heidelberg: IEEE Computer Society, 2008. s. 263-268. ISBN: 978-1-4244-1960-9.
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• 2007

  KOŠEK, M.; KOŘENEK, J. FLOWCONTEXT: Flexible Platform for Multigigabit Stateful Packet Processing. In 2007 International Conference on Field Programmable Logic and Applications. Los Alamitos: IEEE Computer Society, 2007. s. 804-807. ISBN: 978-1-4244-1059- 0.
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  KOBIERSKÝ, P., KOŘENEK, J., HANK, A. Traffic Scanner. Příbram: CESNET, zájmové sdružení právnických osob, 2007. s. 55-67. ISBN: 978-80-239-9285- 4.
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  TOBOLA, J.; KOTÁSEK, Z.; KOŘENEK, J.; MARTÍNEK, T.; STRAKA, M. Online Protocol Testing for FPGA Based Fault Tolerant Systems. In 10th EUROMICRO Conference on Digital System Design DSD 2007. Lubeck, Germany: IEEE Computer Society, 2007. s. 676-679. ISBN: 0-7695-2978- X.
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  KOŘENEK, J.; KOBIERSKÝ, P. Intrusion Detection System Intended for Multigigabit Networks. In 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems. Krakow: IEEE Computer Society, 2007. s. 361-364. ISBN: 978-1-4244-1161- 0.
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• 2006

  ČERNÝ, S.; STRUŽKA, P.; KOŘENEK, J.; MARTÍNEK, T.; KOTÁSEK, Z. FPGA Components in Simulink. In Proceedings of XXVIIIth International Autumn Colloquium ASIS 2006. Ostrava: 2006. s. 158-163. ISBN: 80-86840-26- 3.
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  MARTÍNEK, T.; KOŘENEK, J.; NOVOTNÝ, J. Network Monitoring Adaptor for 10Gbps Technology using FPGA. In CESNET Conference 2006 Proceedings. Prague : CESNET, z. s. p. o.: CESNET National Research and Education Network, 2006. s. 143-151. ISBN: 978-80-239-6533- 9.
  Detail

  MARTÍNEK, T.; LEXA, M.; KOŘENEK, J.; FUČÍK, O. A flexible technique for the automatic design of approximate string matching architectures. In Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. s. 83-84. ISBN: 1-4244-0184- 4.
  Detail

• 2005

  KOŘENEK, J., SEKANINA, L. Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. In Evolvable Systems: From Biology to Hardware. LNCS 3637. Berlin: Springer Verlag, 2005. s. 46-55. ISBN: 978-3-540-28736- 0.
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  ŽÁDNÍK, M., PEČENKA, T., KOŘENEK, J. NetFlow Probe for High- Speed Networks. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL05). Tampere: IEEE Computer Society, 2005. s. 695-698. ISBN: 0-7803-9362- 7.
  Detail | WWW

  MARTÍNEK, T., ZEMČÍK, P., KOŘENEK, J. FPGA-Based Platform for Network Applications. In Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. s. 194-197. ISBN: 9639364487.
  Detail

  KOŘENEK, J. Rychlé vyhledávání regulárních výrazů s využitím FPGA. In Sborník příspěvků ze semináře Počítačové Architektury a Diagnostika. Praha: Fakulta elektrotechniky ČVUT, 2005. s. 1 ( s.)
  Detail

• 2004

  MARTÍNEK, T., KOŘENEK, J., NOVOTNÝ, J. Passive network monitoring adapter intended for 10Gbps technology. In Sborník příspěvků z XXV. konference Europen. Plzeň: Czech Open Systems User' s Group, 2004. s. 55-63. ISBN: 80-86583-07- 4.
  Detail

  ANTOŠ, D.; KOŘENEK, J. String Matching for IPv6 Routers. SOFSEM 2004: Theory and Practice of Computer Science. Praha: CESNET National Research and Education Network, 2004. s. 205-210. ISBN: 80-86732-19-3.
  Detail

  ANTOŠ, D., KOŘENEK, J. Hardware Router' s Lookup Machine and its Formal Verification. In Proceedings of the 3rd International Conference on Networking ICN ' 04. Colmar: University of Haute Alsace, 2004. s. 1002-1007. ISBN: 0-86341-325- 0.
  Detail

• 2003

  ANTOŠ, D.; KOŘENEK, J.; MINAŘÍKOVÁ, K.; ŘEHÁK, V. Packet header matching in Combo6 IPv6 router. Brno: CESNET, 2003. s. 0 ( s.)
  Detail | WWW

• 2002

  KOŘENEK, J. Decomposition for parallel parsing. Proceedings of 8th conference and competition STUDENT EEICT 2002. Brno: Brno University of Technology, 2002. s. 186-188. ISBN: 80-214-2114-2.
  Detail

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