Project detail

Manufacturable and Dependable Multicore Architectures at Nanoscale

Duration: 15.06.2011 — 31.12.2015

Funding resources

Ministerstvo školství, mládeže a tělovýchovy ČR - COST

- whole funder (2011-06-15 - 2015-12-31)

On the project

Constant advances in manufacturing yield and field reliability are important enabling factors for electronic devices pervading our lives, from medical to consumer electronics, from railways to the automotive and avionics scenarios. At the same time, both technology and architectures are today at a turning point. These manufacturability and dependability issues will be resolved efficiently only if a cross-layer approach that takes into account technology, circuit and architectural aspects will be developed. The project has these goals and steps of research: 1) Development and implementation of a new methodology for fault tolerant systems design into FPGA including error detection, faults localization, reconfiguration and synchronization after reconfiguration process. 2) Development and implementation of a new methodology for automated generation of diagnostic resources for on-line testing of FPGA based systems. 3) Development of techniques for the verification of fault tolerant systems quality together with SEU injector tool to be used for reconfigurable platforms. 4) Experimental evaluation of the methodology. 5) The analysis of project results.

Description in Czech
Neustálé pokroky v novodobém průmyslu kladou vyšší požadavky na spolehlivost elektronických zařízení, a to jak od běžné spotřební elektroniky, tak po letecký průmysl. Zároveň jak technologie tak i architektury se dostaly do bodu možného obratu, jsou prezentovány zcela nové myšlenky. Problém výroby a spolehlivosti budou řešitelné pouze tehdy, pokud budou různé aspekty vzaty v potaz jako celek. Projekt má tyto cíle a kroky řešení: 1) Vývoj a implementace nové metodiky návrh systémů odolných proti poruchám do FPGA včetně detekce poruch, lokalizace poruchy, rekonfigurace a synchronizace po rekonfiguraci. 2)  Vývoj a implementaci nové metodiky pro automatické generování diagnostických komponent pro on-line testování systémů implementovaných do FPGA. 3) Vývoj technik pro ověření kvality návrhu systémů odolných proti poruchám, vývoj injektoru SEU poruch použitelné pro rekonfigurovatelné platformy.  4) Experimentální ověření metodiky. 5) Analýza výsledků projektu.

Keywords
dependability, multicore, architectures, nanoscale, digital circuit, checker, fault tolerant system, SEU, simulation, generator, testing, verification, FPGA, reconfiguration, controller, methodology

Key words in Czech
číslicový obvod, hlídací obvody, systémy odolné proti poruchám, SEU, simulace, generátor, testování, verifikace, FPGA, rekonfigurace, řadič, metodika

Mark

COST IC1103

Default language

English

People responsible

Kotásek Zdeněk, doc. Ing., CSc. - principal person responsible

Units

Department of Computer Systems
- beneficiary (2012-03-08 - 2015-12-31)

Results

KAŠTIL, J.; STRAKA, M.; MIČULKA, L.; KOTÁSEK, Z. Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012. p. 250-257. ISBN: 978-0-7695-4798-5.
Detail

PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Radiation Impact on Mechanical Application Driven by FPGA-based Controller. Proceedings of The Fourth Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015. p. 13-16.
Detail

MIČULKA, L.; KOTÁSEK, Z. Synchronization Technique for TMR System After Dynamic Reconfiguration on FPGA. The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2013). Avignon: Politecnico di Milano, 2013. p. 53-56. ISBN: 978-2-11-129175-1.
Detail

ZACHARIÁŠOVÁ, M.; BOLCHINI, C.; KOTÁSEK, Z. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. Proceedings of The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Avignon: COST, European Cooperation in Science and Technology, 2013. p. 35-38. ISBN: 978-2-11-129175-1.
Detail

ZACHARIÁŠOVÁ, M. New Methods for Increasing Efficiency and Speed of Functional Verification. Počítačové architektury a diagnostika PAD 2013. Plzeň: University of West Bohemia in Pilsen, 2013. p. 111-116. ISBN: 978-80-261-0270-0.
Detail

KOTÁSEK, Z.; MIČULKA, L. Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. p. 171-174. ISBN: 978-0-7695-5074-9.
Detail

PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Complex Control System for Testing Fault-Tolerance Methodologies. Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Dresden: COST, European Cooperation in Science and Technology, 2014. p. 24-27. ISBN: 978-2-11-129175-1.
Detail

ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Solving of Constraint Satisfaction Problem. Proceedings of the 20th Conference STUDENT EEICT 2014. Volume 3. Brno: Faculty of Information Technology BUT, 2014. p. 291-295. ISBN: 978-80-214-4924-4.
Detail

PODIVÍNSKÝ, J. Testing Fault-Tolerance Properties in FPGA based Electro-mechanical Applications. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. p. 13-18. ISBN: 978-80-7494-027-9.
Detail

PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 312-319. ISBN: 978-1-4799-5793-4.
Detail

MATUŠOVÁ, L.; KAŠTIL, J.; KOTÁSEK, Z. Automatic Construction of On-line Checking Circuits Based on Finite Automata. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 326-332. ISBN: 978-0-7695-5074-9.
Detail

ZACHARIÁŠOVÁ, M. Application of Evolutionary Computing for Optimization of Functional Verification. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. p. 135-140. ISBN: 978-80-7494-027-9.
Detail

ČEKAN, O. Universal Generation of Test Vectors for Functional Verification. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. p. 44-49. ISBN: 978-80-7494-027-9.
Detail

PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; ČEKAN, O.; KOTÁSEK, Z. FPGA Prototyping and Accelerated Verification of ASIPs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. p. 145-148. ISBN: 978-1-4799-6780-3.
Detail

KRČMA, M.; KAŠTIL, J.; KOTÁSEK, Z. Mapping trained neural networks to FPNNs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. p. 157-160. ISBN: 978-1-4799-6779-7.
Detail

ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Automation and Optimization of Coverage-driven Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 87-94. ISBN: 978-1-4673-8035-5.
Detail

ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Software Fault Tolerance: the Evaluation by Functional Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 284-287. ISBN: 978-1-4673-8035-5.
Detail

ČEKAN, O. Principy generování verifikačních stimulů. Počítačové architektury a diagnostika PAD 2015. Zlín: Fakulta aplikované informatiky, Univerzita Tomáše Bati ve Zlíně, 2015. s. 13-18. ISBN: 978-80-7454-522-1.
Detail

KRČMA, M.; KOTÁSEK, Z.; KAŠTIL, J. Fault Tolerant Field Programmable Neural Networks. In 1st IEEE Nordic Circuits and Systems (NORCAS) Conference. Oslo: IEEE Computer Society, 2015. p. 1-4. ISBN: 978-1-4673-6575-8.
Detail

PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. Microprocessors and Microsystems, 2015, vol. 39, no. 8, p. 1215-1230. ISSN: 0141-9331.
Detail

ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Universal Pseudo-random Generation of Assembler Codes for Processors. Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015. p. 70-73.
Detail

ZACHARIÁŠOVÁ, M.; BOLCHINI, C.; KOTÁSEK, Z. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Karlovy Vary: IEEE Computer Society, 2013. p. 275-278. ISBN: 978-1-4673-6133-0.
Detail

Responsibility: Kotásek Zdeněk, doc. Ing., CSc.