Publikace

• 2024

  HUSA, J.; SEKANINA, L. Semantic Mutation Operator for Fast and Efficient Design of Bent Boolean Functions. Genetic Programming and Evolvable Machines, 2024, roč. 25, č. 3, s. 1-32. ISSN: 1389-2576.
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  VAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). Valencia: Institute of Electrical and Electronics Engineers, 2024. s. 1-6. ISBN: 979-8-3503-4859-0.
  Detail

  KLHŮFEK, J.; ŠAFÁŘ, M.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Exploiting Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. In 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS). Kielce: Institute of Electrical and Electronics Engineers, 2024. s. 1-6. ISBN: 979-8-3503-5934-3.
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  ARIF, M.; REHMAN, F.; SEKANINA, L.; MALIK, A. A comprehensive survey of evolutionary algorithms and metaheuristics in brain EEG-based applications. Journal of Neural Engineering, 2024, roč. 21, č. 5, s. 1-25. ISSN: 1741-2552.
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• 2023

  SEKANINA, L.; MRÁZEK, V.; PIŇOS, M. Hardware-Aware Evolutionary Approaches to Deep Neural Networks. In Handbook of Evolutionary Machine Learning. Genetic and Evolutionary Computation. Singapore: Springer Nature Singapore, 2023. s. 367-396. ISBN: 978-981-9938-13-1.
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  HURTA, M.; SCHWARZEROVÁ, J.; NAGELE, T.; WECKWERTH, W.; PROVAZNÍK, V.; SEKANINA, L. Utilizing Genetic Programming to Enhance Polygenic Risk Score Calculation. In 2023 IEEE International Conference on Bioinformatics and Biomedicine (BIBM 2023). Istanbul: Institute of Electrical and Electronics Engineers, 2023. s. 3782-3787. ISBN: 979-8-3503-3748-8.
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  PIŇOS, M.; MRÁZEK, V.; SEKANINA, L. Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. In 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Talinn: Institute of Electrical and Electronics Engineers, 2023. s. 45-50. ISBN: 979-8-3503-3277-3.
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  LOJDA, J.; PÁNEK, R.; SEKANINA, L.; KOTÁSEK, Z. Automated Design and Usage of the Fault-Tolerant Dynamic Partial Reconfiguration Controller for FPGAs. Microelectronics Reliability, 2023, roč. 2023, č. 144, s. 1-16. ISSN: 0026-2714.
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  JŮZA, T.; SEKANINA, L. GPAM: Genetic Programming with Associative Memory. In 26th European Conference on Genetic Programming (EuroGP) Held as Part of EvoStar. Lecture Notes in Computer Science. LNCS. Cham: Springer Nature Switzerland AG, 2023. s. 68-83. ISBN: 978-3-031-29572-0. ISSN: 0302-9743.
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  HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). Antwerp: Institute of Electrical and Electronics Engineers, 2023. s. 1-2. ISBN: 978-3-9819263-7-8.
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  PIŇOS, M.; MRÁZEK, V.; VAVERKA, F.; VAŠÍČEK, Z.; SEKANINA, L. Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2023, roč. 13, č. 1, s. 212-224. ISSN: 2156-3357.
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  HUSA, J.; SEKANINA, L. Semantic Mutation Operator for Fast and Efficient Design of Bent Boolean Functions. Evo* 2023 -- Late-Breaking Abstracts Volume. Brno: 2023. s. 0-0.
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  HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. In 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Tallinn: Institute of Electrical and Electronics Engineers, 2023. s. 155-160. ISBN: 979-8-3503-3277-3.
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  HURTA, M.; SCHWARZEROVÁ, J.; PROVAZNÍK, V.; WECKWERTH, W.; WALTHER, D.; SEKANINA, L. Utilizing Cartesian Genetic Programming for Efficient Polygenic Risk Score Calculation in Plants. Program and Abstract Book: Swedish Bioinformatics Workshop 2023. Stockholm: 2023. s. 49-49.
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  HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. Multi-objective Design of Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. Evo* 2023 -- Late-Breaking Abstracts Volume. Brno: 2023. s. 0-0.
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  PRABAKARAN, B.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; SHAFIQUE, M. Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). San Francisco: Institute of Electrical and Electronics Engineers, 2023. s. 1-9. ISBN: 979-8-3503-1559-2.
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  SEDLÁČEK, M.; SEKANINA, L. Evolution of Editing Scripts From Examples. In Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '23). Lisbon: Association for Computing Machinery, 2023. s. 803-806. ISBN: 979-8-4007-0120-7.
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• 2022

  BOSIO, A.; DI CARLO, S.; GIRARD, P.; RUOSPO, A.; SANCHEZ, E.; SAVINO, A.; SEKANINA, L.; TRAIOLA, M.; VAŠÍČEK, Z.; VIRAZEL, A. Design, Verification, Test, and In-Field Implications of Approximate Digital Integrated Circuits. In Approximate Computing Techniques. Cham: Springer International Publishing, 2022. s. 349-385. ISBN: 978-3-030-94704-0.
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  SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Inexact Arithmetic Operators. In Approximate Computing Techniques. Cham: Springer International Publishing, 2022. s. 81-107. ISBN: 978-3-030-94704-0.
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  HURTA, M.; DRAHOŠOVÁ, M.; SEKANINA, L.; SMITH, S.; ALTY, J. Evolutionary Design of Reduced Precision Levodopa-Induced Dyskinesia Classifiers. In Genetic Programming, 25th European Conference, EuroGP 2022. Lecture Notes in Computer Science. Madrid: Springer Nature Switzerland AG, 2022. s. 85-101. ISBN: 978-3-031-02055-1.
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  PIŇOS, M.; MRÁZEK, V.; SEKANINA, L. Evolutionary Approximation and Neural Architecture Search. Genetic Programming and Evolvable Machines, 2022, roč. 23, č. 3, s. 351-374. ISSN: 1389-2576.
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  ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z.; VOJNAR, T. SagTree: Towards Efficient Mutation in Evolutionary Circuit Approximation. Swarm and Evolutionary Computation, 2022, roč. 69, č. 100986, s. 1-10. ISSN: 2210-6502.
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  VÁLEK, M.; SEKANINA, L. Evolutionary Approximation in Non-Local Means Image Filters. In 2022 IEEE International Conference on Systems, Man, and Cybernetics (SMC). Praha: Institute of Electrical and Electronics Engineers, 2022. s. 2759-2766. ISBN: 978-1-6654-5258-8.
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• 2021

  SHAFIQUE, M.; STEININGER, A.; SEKANINA, L.; KRSTIĆ, M.; STOJANOVIC, G.; MRÁZEK, V. 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. USA: Institute of Electrical and Electronics Engineers, 2021. s. 0-0. ISBN: 978-1-6654-3595-6.
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  SEKANINA, L. Evolutionary Algorithms in Approximate Computing: A Survey. Journal of Integrated Circuits and Systems, 2021, roč. 16, č. 2, s. 1-12. ISSN: 1872-0234.
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  PIŇOS, M.; MRÁZEK, V.; SEKANINA, L. Evolutionary Neural Architecture Search Supporting Approximate Multipliers. In Genetic Programming, 24th European Conference, EuroGP 2021. Lecture Notes in Computer Science, vol 12691. Seville: Springer Nature Switzerland AG, 2021. s. 82-97. ISBN: 978-3-030-72812-0.
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  SEKANINA, L. Neural Architecture Search and Hardware Accelerator Co-Search: A Survey. IEEE Access, 2021, roč. 9, č. 9, s. 151337-151362. ISSN: 2169-3536.
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  BARBARESCHI, M.; BOSIO, A.; SEKANINA, L.; BRAUN, C. Editorial: Special issue on Advancing on Approximate Computing: Methodologies, Architectures and Algorithms. Future Generation Computer Systems-The International Journal of Grid Computing Theory Methods and Applications. 2021. s. 54-55. ISSN: 0167-739X.
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• 2020

  HU, T.; NICOLAU, M.; SEKANINA, L. Special issue on highlights of genetic programming 2019 events. Genetic Programming and Evolvable Machines. 2020. s. 283-285. ISSN: 1389-2576.
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  BOSIO, A.; DI CARLO, S.; GIRARD, P.; SANCHEZ, E.; SAVINO, A.; SEKANINA, L.; TRAIOLA, M.; VAŠÍČEK, Z.; VIRAZEL, A. Design, Verification, Test and In-Field Implications of Approximate Computing Systems. In 25th IEEE European Test Symposium. Los Alamitos: Institute of Electrical and Electronics Engineers, 2020. s. 1-10. ISBN: 978-1-7281-4312-5.
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  ANSARI, M.; MRÁZEK, V.; COCKBURN, B.; SEKANINA, L.; VAŠÍČEK, Z.; HAN, J. Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. on VLSI Systems., 2020, roč. 28, č. 2, s. 317-328. ISSN: 1063-8210.
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  VAVERKA, F.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: Institute of Electrical and Electronics Engineers, 2020. s. 294-297. ISBN: 978-3-9819263-4-7.
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  HUSA, J.; SEKANINA, L. Evolving Cryptographic Boolean Functions with Minimal Multiplicative Complexity. In 2020 IEEE Congress on Evolutionary Computation (CEC). Los Alamitos: IEEE Computational Intelligence Society, 2020. s. 1-8. ISBN: 978-1-7281-6929-3.
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  PRABAKARAN, B.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; SHAFIQUE, M. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. In 2020 57th ACM/IEEE Design Automation Conference (DAC). San Francisco: Institute of Electrical and Electronics Engineers, 2020. s. 1-6. ISBN: 978-1-4503-6725-7.
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  ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z.; VOJNAR, T. Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. APPLIED SOFT COMPUTING, 2020, roč. 95, č. 106466, s. 1-17. ISSN: 1568-4946.
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  MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z. Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2020, roč. 10, č. 4, s. 406-418. ISSN: 2156-3357.
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  GROCHOL, D.; SEKANINA, L. Evolutionary Design of Hash Functions for IPv6 Network Flow Hashing. In IEEE Congress on Evolutionary Computation. Los Alamitos: IEEE Computational Intelligence Society, 2020. s. 1-8. ISBN: 978-1-7281-6929-3.
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  MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z. Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. In 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems. Genoa: Institute of Electrical and Electronics Engineers, 2020. s. 243-247. ISBN: 978-1-7281-4922-6.
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• 2019

  SEKANINA, L.; HU, T.; LOURENÇO, N.; RICHTER, H.; GARCÍA-SÁNCHEZ, P. Genetic Programming 22nd European Conference. Lecture Notes in Computer Science. Cham: Springer International Publishing, 2019. s. 0-0. ISBN: 978-3-030-16669-4.
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  SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Automated Search-Based Functional Approximation for Digital Circuits. In Approximate Circuits - Methodologies and CAD. Heidelberg: Springer International Publishing, 2019. s. 175-203. ISBN: 978-3-319-99322-5.
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  STAMENKOVIC, Z.; BOSIO, A.; CSEREY, G.; NOVÁK, O.; PLESKACZ, W.; SEKANINA, L.; STEININGER, A.; STOJANOVIC, G.; STOPJAKOVÁ, V. International Symposium on Design and Diagnostics of Electronic Circuits and Systems. In 2019 IEEE International Test Conference. Washington, DC: Institute of Electrical and Electronics Engineers, 2019. s. 1-4. ISBN: 978-1-7281-4823-6.
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  VAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Automated Circuit Approximation Method Driven by Data Distribution. In Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019. s. 96-101. ISBN: 978-3-9819263-2-3.
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  REK, P.; SEKANINA, L. TypeCNN: CNN Development Framework With Flexible Data Types. In Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019. s. 292-295. ISBN: 978-3-9819263-2-3.
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  MRÁZEK, V.; HANIF, M.; VAŠÍČEK, Z.; SEKANINA, L.; SHAFIQUE, M. autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. In The 56th Annual Design Automation Conference 2019 (DAC '19). Las Vegas: Association for Computing Machinery, 2019. s. 1-6. ISBN: 978-1-4503-6725-7.
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  DRAHOŠOVÁ, M.; SEKANINA, L.; WIGLASZ, M. Adaptive Fitness Predictors in Coevolutionary Cartesian Genetic Programming. EVOLUTIONARY COMPUTATION, 2019, roč. 27, č. 3, s. 497-523. ISSN: 1063-6560.
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  MRÁZEK, V.; SEKANINA, L.; DOBAI, R.; SÝS, M.; ŠVENDA, P. Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Trans. on VLSI Systems., 2019, roč. 27, č. 12, s. 2734-2744. ISSN: 1063-8210.
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  MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; HANIF, M.; SHAFIQUE, M. ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Denver: Institute of Electrical and Electronics Engineers, 2019. s. 1-8. ISBN: 978-1-7281-2350-9.
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  BADÁŇ, F.; SEKANINA, L. Optimizing Convolutional Neural Networks for Embedded Systems By Means of Neuroevolution. In Theory and Practice of Natural Computing. LNCS 11934. Cham: Springer International Publishing, 2019. s. 109-121. ISBN: 978-3-030-34499-3.
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  KONČAL, O.; SEKANINA, L. Cartesian Genetic Programming as an Optimizer of Programs Evolved with Geometric Semantic Genetic Programming. In Genetic Programming 22nd European Conference, EuroGP 2019. Cham: Springer International Publishing, 2019. s. 98-113. ISBN: 978-3-030-16669-4.
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• 2018

  CASTELLI, M.; SEKANINA, L.; ZHANG, M.; CAGNONI, S.; GARCÍA-SÁNCHEZ, P. 21st European Conference on Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2018. s. 0-0. ISBN: 978-3-319-77552-4.
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  SEKANINA, L.; VAŠÍČEK, Z.; BOSIO, A.; TRAIOLA, M.; RECH, P.; OLIVEIRA, D.; FERNANDES, F.; DI CARLO, S. Special Session: How Approximate Computing impacts Verification, Test and Reliability. 2018 IEEE 36th VLSI Test Symposium. San Francisco: IEEE Computer Society, 2018. s. 0-0. ISBN: 978-1-5386-3774-6.
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  TREFZER, M.; SEKANINA, L. Guest Editorial: Bio-inspired Hardware and Evolvable Systems. IET Computers and Digital Techniques. 2018. s. 121-121. ISSN: 1751-8601.
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  SEKANINA, L.; MRÁZEK, V.; VAŠÍČEK, Z. Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. In 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). Bordeaux: IEEE Circuits and Systems Society, 2018. s. 377-380. ISBN: 978-1-5386-9562-3.
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  SEKANINA, L. Approximate Computing: An Old Job for Cartesian Genetic Programming?. In Inspired by Nature. Emergence, Complexity and Computation, Vol. 28. Cham: Springer International Publishing, 2018. s. 195-212. ISBN: 978-3-319-67996-9.
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  ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; VOJNAR, T. ADAC: Automated Design of Approximate Circuits. In Proceedings of 30th International Conference on Computer Aided Verification (CAV'18). Oxford, UK: Springer International Publishing, 2018. s. 612-620. ISBN: 978-3-319-96145-3.
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  WIGLASZ, M.; SEKANINA, L. Cooperative Coevolutionary Approximation in HOG-based Human Detection Embedded System. In 2018 IEEE Symposium Series on Computational Intelligence (SSCI 2018). Bengaluru: Institute of Electrical and Electronics Engineers, 2018. s. 1313-1320. ISBN: 978-1-5386-9276-9.
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  MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; JIANG, H.; HAN, J. Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. on VLSI Systems., 2018, roč. 26, č. 11, s. 2572-2576. ISSN: 1063-8210.
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  MRÁZEK, V.; SÝS, M.; VAŠÍČEK, Z.; SEKANINA, L.; MATYÁŠ, V. Evolving Boolean Functions for Fast and Efficient Randomness Testing. In Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '18). Kyoto: Association for Computing Machinery, 2018. s. 1302-1309. ISBN: 978-1-4503-5618-3.
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  GROCHOL, D.; SEKANINA, L. Fast Reconfigurable Hash Functions for Network Flow Hashing in FPGAs. In Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh: Institute of Electrical and Electronics Engineers, 2018. s. 257-263. ISBN: 978-1-5386-7753-7.
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  MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. In Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh: Institute of Electrical and Electronics Engineers, 2018. s. 264-271. ISBN: 978-1-5386-7753-7.
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  GROCHOL, D.; SEKANINA, L. Multi-Objective Evolution of Ultra-Fast General-Purpose Hash Functions. In European Conference on Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2018. s. 187-202. ISBN: 978-3-319-77553-1.
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• 2017

  SHAFIQUE, M.; HAFIZ, R.; JAVED, M.; ABBAS, S.; SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In 2017 IEEE Computer Society Annual Symposium on VLSI. Los Alamitos: IEEE Computer Society Press, 2017. s. 627-632. ISBN: 978-1-5090-6762-6.
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  SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Approximate Circuits in Low-Power Image and Video Processing: The Approximate Median Filter. Radioengineering, 2017, roč. 26, č. 3, s. 623-632. ISSN: 1210-2512.
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  MCDERMOTT, J.; CASTELLI, M.; SEKANINA, L.; HAASDIJK, E.; GARCÍA-SÁNCHEZ, P. 20th European Conference on Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2017. s. 0-0. ISBN: 978-3-319-55696-3.
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  MRÁZEK, V.; HRBÁČEK, R.; VAŠÍČEK, Z.; SEKANINA, L. EvoApprox8b: Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods. In Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017. s. 258-261. ISBN: 978-3-9815370-9-3.
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  VAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Towards Low Power Approximate DCT Architecture for HEVC Standard. In Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017. s. 1576-1581. ISBN: 978-3-9815370-9-3.
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  WIGLASZ, M.; SEKANINA, L. Evolutionary Approximation of Gradient Orientation Module in HOG-based Human Detection System. In 2017 IEEE Global Conference on Signal and Information Processing GlobalSIP 2017. Montreal: IEEE Signal Processing Society, 2017. s. 1300-1304. ISBN: 978-1-5090-5989-8.
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  DOBAI, R.; KOŘENEK, J.; SEKANINA, L. Evolutionary design of hash function pairs for network filters. APPLIED SOFT COMPUTING, 2017, roč. 56, č. 7, s. 173-181. ISSN: 1568-4946.
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  GROCHOL, D.; SEKANINA, L. Comparison of Parallel Linear Genetic Programming Implementations. In Recent Advances in Soft Computing: Proceedings of the 22nd International Conference on Soft Computing (MENDEL 2016) held in Brno, Czech Republic, at June 8-10, 2016. Cham: Springer International Publishing, 2017. s. 64-76. ISBN: 978-3-319-58088-3.
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  GROCHOL, D.; SEKANINA, L. Multiobjective Evolution of Hash Functions for High Speed Networks. In Proceedings of the 2017 IEEE Congress on Evolutionary Computation. San Sebastian: IEEE Computer Society, 2017. s. 1533-1540. ISBN: 978-1-5090-4600-3.
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  KEŠNER, F.; SEKANINA, L.; BRÁZDIL, M. Modular Framework for Detection of Inter-ictal Spikes in iEEG. In The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC'17). Los Alamos: Institute of Electrical and Electronics Engineers, 2017. s. 418-421. ISBN: 978-1-5090-2809-2.
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  ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; VOJNAR, T. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017. s. 416-423. ISBN: 978-1-5386-3093-8.
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  MINAŘÍK, M.; SEKANINA, L. On Evolutionary Approximation of Sigmoid Function for HW/SW Embedded Systems. In 20th European Conference on Genetic Programming, EuroGP 2017. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2017. s. 343-358. ISBN: 978-3-319-55696-3.
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• 2016

  SEKANINA, L. Introduction to Approximate Computing: Embedded Tutorial. In 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Košice: Institute of Electrical and Electronics Engineers, 2016. s. 90-95. ISBN: 978-1-5090-2467-4.
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  SEKANINA, L.; KAPUSTA, V. Visualisation and Analysis of Genetic Records Produced by Cartesian Genetic Programming. In GECCO'16 Companion. New York: Association for Computing Machinery, 2016. s. 1411-1418. ISBN: 978-1-4503-4323-7.
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  SEKANINA, L.; VAŠÍČEK, Z. Genetic Improvement for Approximate Computing. 2nd Workshop on Approximate Computing (WAPCO 2016). Prague: 2016. s. 1-2.
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  MRÁZEK, V.; SARWAR, S.; SEKANINA, L.; VAŠÍČEK, Z.; ROY, K. Design of Power-Efficient Approximate Multipliers for Approximate Artificial Neural Networks. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Austin, TX: Association for Computing Machinery, 2016. s. 811-817. ISBN: 978-1-4503-4466-1.
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  GROCHOL, D.; SEKANINA, L.; KOŘENEK, J.; ŽÁDNÍK, M.; KOŠAŘ, V. Evolutionary Circuit Design for Fast FPGA-Based Classification of Network Application Protocols. APPLIED SOFT COMPUTING, 2016, roč. 38, č. 1, s. 933-941. ISSN: 1568-4946.
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  VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Design of Complex Approximate Combinational Circuits. Genetic Programming and Evolvable Machines, 2016, roč. 17, č. 2, s. 169-192. ISSN: 1389-2576.
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  HOLÍK, L.; LENGÁL, O.; ROGALEWICZ, A.; SEKANINA, L.; VAŠÍČEK, Z.; VOJNAR, T. Towards Formal Relaxed Equivalence Checking in Approximate Computing Methodology. 2nd Workshop on Approximate Computing (WAPCO 2016). Prague: 2016. s. 1-6.
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  DVOŘÁČEK, P.; SEKANINA, L. Evolutionary Approximation of Edge Detection Circuits. In 19th European Conference on Genetic programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2016. s. 19-34. ISBN: 978-3-319-30667-4.
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  GROCHOL, D.; SEKANINA, L. Evolutionary Design of Fast High-quality Hash Functions for Network Applications. In GECCO '16 Proceedings of the 2016 on Genetic and Evolutionary Computation Conference. New York, NY: Association for Computing Machinery, 2016. s. 901-908. ISBN: 978-1-4503-4206-3.
  Detail | WWW

  VAŠÍČEK, Z.; SEKANINA, L. Search-based synthesis of approximate circuits implemented into FPGAs. In 26th International Conference on Field Programmable Logic and Applications. Lausanne: Institute of Electrical and Electronics Engineers, 2016. s. 1-4. ISBN: 978-2-8399-1844-2.
  Detail | WWW

  DOBAI, R.; KOŘENEK, J.; SEKANINA, L. Adaptive Development of Hash Functions in FPGA-Based Network Routers. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: IEEE Computational Intelligence Society, 2016. s. 1-8. ISBN: 978-1-5090-4240-1.
  Detail | WWW

  VAVERKA, F.; HRBÁČEK, R.; SEKANINA, L. Evolving Component Library for Approximate High Level Synthesis. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: IEEE Computational Intelligence Society, 2016. s. 1-8. ISBN: 978-1-5090-4240-1.
  Detail | WWW

  VAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Evolutionary Functional Approximation of Circuits Implemented into FPGAs. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016. s. 1-8. ISBN: 978-1-5090-4240-1.
  Detail | WWW

  SÁNCHEZ-CLEMENTE, A.; ENTRENA, L.; HRBÁČEK, R.; SEKANINA, L. Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. IEEE TRANSACTIONS ON RELIABILITY, 2016, roč. 65, č. 4, s. 1871-1883. ISSN: 0018-9529.
  Detail | WWW

• 2015

  SEKANINA, L. Principles and Applications of Polymorphic Circuits. In Evolvable Hardware - From Practice to Application. Berlin: Springer Verlag, 2015. s. 209-224. ISBN: 978-3-662-44615-7.
  Detail

  SEKANINA, L.; VAŠÍČEK, Z. Functional Equivalence Checking for Evolution of Complex Digital Circuits. In Evolvable Hardware - From Practice to Application. Berlin: Springer Verlag, 2015. s. 175-189. ISBN: 978-3-662-44615-7.
  Detail

  SEKANINA, L.; VAŠÍČEK, Z. Evolutionary Computing in Approximate Circuit Design and Optimization. 1st Workshop on Approximate Computing (WAPCO 2015). Amsterdam: 2015. s. 1-6.
  Detail | WWW

  PETRLÍK, J.; SEKANINA, L. Towards Robust and Accurate Traffic Prediction Using Parallel Multiobjective Genetic Algorithms and Support Vector Regression. In 2015 IEEE 18th International Conference on Intelligent Transportation Systems. Los Alamitos: IEEE Computer Society, 2015. s. 2231-2236. ISBN: 978-1-4673-6596-3.
  Detail | WWW

  DOBAI, R.; SEKANINA, L. Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware. ACM Transactions on Reconfigurable Technology and Systems, 2015, roč. 8, č. 3, s. 1-24. ISSN: 1936-7406.
  Detail | WWW

  KEŠNER, F.; CIMBÁLNÍK, J.; DOLEŽALOVÁ, I.; BRÁZDIL, M.; SEKANINA, L. Fast Automated Interictal Spike Detection in iEEG/ECoG Recordings. Proceedings of NEUROTECHNIX: International Congress on Neurotechnology, Electronics and Informatics. Lisabon: 2015. s. 1-4.
  Detail

  VAŠÍČEK, Z.; SEKANINA, L. Circuit Approximation Using Single- and Multi-Objective Cartesian GP. In Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. s. 217-229. ISBN: 978-3-319-16500-4.
  Detail | WWW

  GROCHOL, D.; SEKANINA, L.; ŽÁDNÍK, M.; KOŘENEK, J. A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. In Applications of Evolutionary Computation, 18th European Conference. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. s. 67-78. ISBN: 978-3-319-16548-6.
  Detail | WWW

  DRAHOŠOVÁ, M.; HULVA, J.; SEKANINA, L. Indirectly Encoded Fitness Predictors Coevolved with Cartesian Programs. In Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. s. 113-125. ISBN: 978-3-319-16500-4.
  Detail | WWW

  VAŠÍČEK, Z.; SEKANINA, L. Evolutionary approximation of complex digital circuits. In Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. New York: Association for Computing Machinery, 2015. s. 1505-1506. ISBN: 978-1-4503-3488-4.
  Detail

  MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Approximation of Software for Embedded Systems: Median Function. In GECCO Companion '15 Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. ACM. New York: Association for Computing Machinery, 2015. s. 795-801. ISBN: 978-1-4503-3488-4.
  Detail | WWW

  VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Approach to Approximate Digital Circuits Design. IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, 2015, roč. 19, č. 3, s. 432-444. ISSN: 1089-778X.
  Detail | WWW

• 2014

  SEKANINA, L.; VAŠÍČEK, Z. On Evolutionary Approximation of Logic Circuits. In Computing with New Resources. Berlin: Springer Verlag, 2014. s. 367-378. ISBN: 978-3-319-13349-2.
  Detail | WWW

  SEKANINA, L.; PTÁK, O.; VAŠÍČEK, Z. Cartesian Genetic Programming as Local Optimizer of Logic Networks. In 2014 IEEE Congress on Evolutionary Computation. Beijing: IEEE Computational Intelligence Society, 2014. s. 2901-2908. ISBN: 978-1-4799-1488-3.
  Detail | WWW

  PETRLÍK, J.; FUČÍK, O.; SEKANINA, L. Multiobjective Selection of Input Sensors for SVR Applied to Road Traffic Prediction. In Parallel Problem Solving from Nature - PPSN XIII. Lecture Notes in Computer Science. Heidelberg: Springer Verlag, 2014. s. 802-811. ISBN: 978-3-319-10761-5.
  Detail

  DRAHOŠOVÁ, M.; KOMJÁTHY, G.; SEKANINA, L. Towards Compositional Coevolution in Evolutionary Circuit Design. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. s. 157-164. ISBN: 978-1-4799-4479-8.
  Detail | WWW

  VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Design of Approximate Multipliers Under Different Error Metrics. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warsaw: IEEE Computer Society, 2014. s. 135-140. ISBN: 978-1-4799-4558-0.
  Detail | WWW

  PETRLÍK, J.; FUČÍK, O.; SEKANINA, L. Multiobjective Selection of Input Sensors for Travel Times Forecasting Using Support Vector Regression. In 2014 IEEE Symposium on Computational Intelligence in Vehicles and Transportation Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. s. 14-21. ISBN: 978-1-4799-4498-9.
  Detail

  DOBAI, R.; GLETTE, K.; TORRESEN, J.; SEKANINA, L. Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in Field Programmable Gate Arrays. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. s. 85-92. ISBN: 978-1-4799-4480-4.
  Detail | WWW

  MINAŘÍK, M.; SEKANINA, L. Exploring the Search Space of Hardware / Software Embedded Systems by Means of GP. In Genetic Programming, 17th European Conference, EuroGP 2014. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2014. s. 112-123. ISBN: 978-3-662-44302-6.
  Detail | WWW

  HRBÁČEK, R.; SEKANINA, L. Towards Highly Optimized Cartesian Genetic Programming: From Sequential via SIMD and Thread to Massive Parallel Implementation. In GECCO '14 Proceedings of the 2014 conference on Genetic and evolutionary computation. New York: Association for Computing Machinery, 2014. s. 1015-1022. ISBN: 978-1-4503-2662-9.
  Detail | WWW

  VAŠÍČEK, Z.; SEKANINA, L. How to Evolve Complex Combinational Circuits From Scratch?. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. s. 133-140. ISBN: 978-1-4799-4480-4.
  Detail | WWW

• 2013

  SALVADOR, R.; OTERO, A.; MORA, J.; DE LA TORRE, E.; RIESGO, T.; SEKANINA, L. Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE TRANSACTIONS ON COMPUTERS, 2013, roč. 62, č. 8, s. 1481-1493. ISSN: 0018-9340.
  Detail

  SEKANINA, L. Ubiquity symposium: Evolutionary computation and the processes of life: evolutionary computation in physical world. Ubiquity, 2013, roč. 2013, č. 2, s. 1-7. ISSN: 1530-2180.
  Detail | WWW

  SEKANINA, L.; RŮŽIČKA, R.; VAŠÍČEK, Z.; ŠIMEK, V.; HANÁČEK, P. Implementing a Unique Chip ID on a Reconfigurable Polymorphic Circuit. Information Technology and Control, 2013, roč. 42, č. 1, s. 7-14. ISSN: 1392-124X.
  Detail | WWW

  SEKANINA, L.; VAŠÍČEK, Z. Approximate Circuit Design by Means of Evolvable Hardware. In 2013 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI). Singapur: IEEE Computer Society, 2013. s. 21-28. ISBN: 978-1-4673-5847-7.
  Detail | WWW

  DOBAI, R.; SEKANINA, L. Image Filter Evolution on the Xilinx Zynq Platform. Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems. Torino: IEEE Circuits and Systems Society, 2013. s. 164-171. ISBN: 978-1-4673-6381-5.
  Detail | WWW

  VAŠÍČEK, Z.; BIDLO, M.; SEKANINA, L. Evolution of efficient real-time non-linear image filters for FPGAs. SOFT COMPUTING, 2013, roč. 17, č. 11, s. 2163-2180. ISSN: 1432-7643.
  Detail

  DOBAI, R.; SEKANINA, L. Towards Evolvable Systems Based on the Xilinx Zynq Platform. 2013 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI). Singapur: IEEE Computational Intelligence Society, 2013. s. 89-95. ISBN: 978-1-4673-5869-9.
  Detail | WWW

  MINAŘÍK, M.; SEKANINA, L. Concurrent Evolution of Hardware and Software for Application-Specific Microprogrammed Systems. 2013 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI). Singapur: IEEE Computational Intelligence Society, 2013. s. 43-50. ISBN: 978-1-4673-5869-9.
  Detail | WWW

  PETRLÍK, J.; SEKANINA, L. Multiobjective evolution of approximate multiple constant multipliers. In IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013. Brno: IEEE Computer Society, 2013. s. 116-119. ISBN: 978-1-4673-6133-0.
  Detail | WWW

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Advanced Approach to Calibration of Traffic Microsimulation Models using Travel Times. Journal of Cellular Automata, 2013, roč. 8, č. 6, s. 457-467. ISSN: 1557-5969.
  Detail | WWW

• 2012

  SEKANINA, L. Evolvable hardware. In Handbook of Natural Computing. Berlin: Springer Verlag, 2012. s. 1657-1705. ISBN: 978-3-540-92909-3.
  Detail

  DRAHOŠOVÁ, M.; SEKANINA, L. Coevolution in Cartesian Genetic Programming. Proc. of the 15th European Conference on Genetic Programming. Lecture Notes in Computer Science. Heidelberg: Springer Verlag, 2012. s. 182-193. ISBN: 978-3-642-29138-8.
  Detail | WWW

  SALVADOR, R.; OTERO, A.; MORA, J.; DE LA TORRE, E.; RIESGO, T.; SEKANINA, L. Implementation Techniques for Evolvable HW Systems: Virtual vs. Dynamic Reconfiguration. Proc. of the 22nd International Conference on Field Programmable Logic and Applications (FPL). Oslo: IEEE Computer Society, 2012. s. 547-550. ISBN: 978-1-4673-2257-7.
  Detail | WWW

  SEKANINA, L.; SALAJKA, V.; VAŠÍČEK, Z. Two-Step Evolution of Polymorphic Circuits for Image Multi-Filtering. In 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012. s. 432-439. ISBN: 978-1-4673-1508-1.
  Detail | WWW

  SMOLKA, T.; ŠVENDA, P.; SEKANINA, L.; MATYÁŠ, V. Evolutionary Design of Message Efficient Secrecy Amplification Protocols. Proc. of the 15th European Conference on Genetic Programming. Lecture Notes in Computer Science. Heidelberg: Springer Verlag, 2012. s. 194-205. ISBN: 978-3-642-29138-8.
  Detail | WWW

  SEKANINA, L.; SALAJKA, V. Towards New Applications of Multi-Function Logic: Image Multi-Filtering. Proc. of the 2012 Design, Automation and Test in Europe. Dresden: European Design and Automation Association, 2012. s. 824-827. ISBN: 978-1-4577-2145-8.
  Detail | WWW

  SEKANINA, L.; VAŠÍČEK, Z. A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits. Proc. of the 2012 Design, Automation and Test in Europe. Dresden: European Design and Automation Association, 2012. s. 715-720. ISBN: 978-1-4577-2145-8.
  Detail | WWW

  PETRLÍK, J.; SEKANINA, L. Multiobjective Evolution of Multiple-Constant Multipliers. Proceedings of the 18th International Conference on Soft Computing (MENDEL2012). Brno: Faculty of Mechanical Engineering BUT, 2012. s. 64-69. ISBN: 978-80-214-4540-6.
  Detail

  ŽALOUDEK, L.; SEKANINA, L. Cellular automata-based systems with fault-tolerance. Natural Computing, 2012, roč. 11, č. 4, s. 673-685. ISSN: 1567-7818.
  Detail

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Evolutionary approach to calibration of cellular automaton based traffic simulation model. In Proceedings of the 15th International IEEE Conference on Intelligent Transportation Systems. Anchorage: IEEE Intelligent Transportation Systems Society, 2012. s. 122-129. ISBN: 978-1-4673-3062-6.
  Detail | WWW

  PETRLÍK, J.; KORČEK, P.; FUČÍK, O.; BESZÉDEŠ, M.; SEKANINA, L. Estimation of traffic density map using evolutionary algorithm. In Proceedings of the 15th International IEEE Conference on Intelligent Transportation Systems. Anchorage: IEEE Intelligent Transportation Systems Society, 2012. s. 632-637. ISBN: 978-1-4673-3062-6.
  Detail | WWW

  DRAHOŠOVÁ, M.; SEKANINA, L. Acceleration of Evolutionary Image Filter Design Using Coevolution in Cartesian GP. Lecture Notes in Computer Science, 2012, roč. 2012, č. 7491, s. 163-172. ISSN: 0302-9743.
  Detail | WWW

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Calibrating Traffic Simulation Model using Vehicle Travel Times. Lecture Notes in Computer Science, 2012, roč. 2012, č. 7495, s. 807-816. ISSN: 0302-9743.
  Detail | WWW

  VAŠÍČEK, Z.; SEKANINA, L. On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming. In 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012. s. 2379-2386. ISBN: 978-1-4673-1508-1.
  Detail | WWW

  SALVADOR, R.; VIDAL, A.; MORENO, F.; RIESGO, T.; SEKANINA, L. Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling. Microprocessors and Microsystems, 2012, roč. 36, č. 5, s. 427-438. ISSN: 0141-9331.
  Detail | WWW

• 2011

  SALVADOR, R.; MORENO, F.; RIESGO, T.; SEKANINA, L. Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems. EURASIP Journal on Advances in Signal Processing, 2011, roč. 2011, č. 2011, s. 1-20. ISSN: 1687-6172.
  Detail | WWW

  SEKANINA, L. Evolutionary hardware design (Invited Paper). VLSI Circuits and Systems V. Proc. of SPIE Vol. 8067. Bellingham: SPIE - the international society for optics and photonics, 2011. s. 1-11. ISBN: 978-0-8194-8656-1.
  Detail | WWW

  SALVADOR, R.; VIDAL, A.; MORENO, F.; RIESGO, T.; SEKANINA, L. Bio-inspired FPGA architecture for self-calibration of an image compression core based on wavelet transforms in embedded systems. VLSI Circuits and Systems V. Proc. of SPIE Vol. 8067. Bellingham: SPIE - the international society for optics and photonics, 2011. s. 1-13. ISBN: 978-0-8194-8656-1.
  Detail

  OTERO, A.; SALVADOR, R.; MORA, J.; DE LA TORRE, E.; RIESGO, T.; SEKANINA, L. A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems. Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2011. s. 336-343. ISBN: 978-1-4577-0599-1.
  Detail

  SALVADOR, R.; OTERO, A.; MORA, J.; DE LA TORRE, E.; RIESGO, T.; SEKANINA, L. Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2011. s. 184-191. ISBN: 978-1-4577-0599-1.
  Detail | WWW

  SEKANINA, L. Evolution of digital circuits. Proceedings of the 2011 GECCO conference companion on Genetic and evolutionary computation. New York: Association for Computing Machinery, 2011. s. 1343-1359. ISBN: 978-1-4503-0690-4.
  Detail | WWW

  SEKANINA, L.; VAŠÍČEK, Z. CGP Acceleration Using Field-Programmable Gate Arrays. In Cartesian Genetic Programming. Natural Computing Series. Berlin: Springer Verlag, 2011. s. 217-230. ISBN: 978-3-642-17309-7.
  Detail | WWW

  SEKANINA, L.; HARDING, S.; BANZHAF, W.; KOWALIW, T. Image Processing and CGP. In Cartesian Genetic Programming. Natural Computing Series. Berlin: Springer Verlag, 2011. s. 181-215. ISBN: 978-3-642-17309-7.
  Detail

  SEKANINA, L.; WALKER, J.; KAUFMANN, P.; PLATZNER, M. Evolution of Electronic Circuits. In Cartesian Genetic Programming. Natural Computing Series. Berlin: Springer Verlag, 2011. s. 125-179. ISBN: 978-3-642-17309-7.
  Detail

  SEKANINA, L.; KOMENDA, T. Global Control in Polymorphic Cellular Automata. Journal of Cellular Automata, 2011, roč. 6, č. 4, s. 301-321. ISSN: 1557-5969.
  Detail | WWW

  SALVADOR, R.; OTERO, A.; MORA, J.; DE LA TORRE, E.; SEKANINA, L.; RIESGO, T. Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. Proc. of the 2011 International Conference on ReConFigurable Computing and FPGAs. Los Alamitos: IEEE Computer Society, 2011. s. 164-169. ISBN: 978-0-7695-4551-6.
  Detail | WWW

  VAŠÍČEK, Z.; SEKANINA, L. A Global Postsynthesis Optimization Method for Combinational Circuits. Proc. of the Design, Automation and Test in Europe DATE 2011. Grenoble: European Design and Automation Association, 2011. s. 1525-1528. ISBN: 978-3-9810801-7-9.
  Detail | WWW

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. A Scalable Cellular Automata Based Microscopic Traffic Simulation. Proceedings of the IEEE Intelligent Vehicles Symposium 2011 (IV11). Baden-Baden: IEEE Intelligent Transportation Systems Society, 2011. s. 13-18. ISBN: 978-1-4577-0889-3.
  Detail | WWW

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Cellular automata based traffic simulation accelerated on GPU. Proceedings of the 17th International Conference on Soft Computing (MENDEL2011). Brno: Institute of Automation and Computer Science FME BUT, 2011. s. 395-402. ISBN: 978-80-214-4302-0.
  Detail | WWW

  RŮŽIČKA, R.; ŠIMEK, V.; SEKANINA, L. Behavior of CMOS Polymorphic Circuits in High Temperature Environment. Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Cottbus: IEEE Computer Society, 2011. s. 447-452. ISBN: 978-1-4244-9753-9.
  Detail | WWW

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Microscopic traffic simulation using CUDA. Advanced Computer Architecture and Compilation for High-Performace and Embedded Systems (ACACES 2011) Poster Abstracts. Fiuggi: Academia Press, 2011. s. 207-210. ISBN: 978-90-382-1798-7.
  Detail

  GAJDA, Z.; SEKANINA, L. On Evolutionary Synthesis of Compact Polymorphic Combinational Circuits. JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING, 2011, roč. 17, č. 6, s. 607-631. ISSN: 1542-3980.
  Detail | WWW

  MINAŘÍK, M.; SEKANINA, L. Evolution of Iterative Formulas Using Cartesian Genetic Programming. Lecture Notes in Computer Science, 2011, roč. 2011, č. 6881, s. 11-20. ISSN: 0302-9743.
  Detail

  VAŠÍČEK, Z.; BIDLO, M.; SEKANINA, L.; GLETTE, K. Evolutionary Design of Efficient and Robust Switching Image Filters. In Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2011. s. 192-199. ISBN: 978-1-4577-0599-1.
  Detail | WWW

  ŽALOUDEK, L.; SEKANINA, L. Increasing Fault-Tolerance in Cellular-Based Systems. Lecture Notes in Computer Science, 2011, roč. 2011, č. 6714, s. 234-245. ISSN: 0302-9743.
  Detail | WWW

  VAŠÍČEK, Z.; SEKANINA, L. Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genetic Programming and Evolvable Machines, 2011, roč. 12, č. 3, s. 305-327. ISSN: 1389-2576.
  Detail | WWW

  GAJDA, Z.; SEKANINA, L. Recent Advances in Evolutionary Synthesis and Optimization of Ordinary and Polymorphic Circuits. Brno: Faculty of Information Technology BUT, 2011. 111 s. ISBN: 978-80-214-4417-1.
  Detail

  VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Optimization of Complex Digital Circuits. 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2011. s. 127-127. ISBN: 978-80-214-4305-1.
  Detail

• 2010

  SALVADOR, R.; MORENO, F.; RIESGO, T.; SEKANINA, L. High level validation of an optimization algorithm for the implementation of adaptive Wavelet Transforms in FPGAs. Proc. of 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2010. s. 96-103. ISBN: 978-0-7695-4171-6.
  Detail

  VAŠÍČEK, Z.; SEKANINA, L.; BIDLO, M. A Method for Design of Impulse Bursts Noise Filters Optimized for FPGA Implementations. DATE 2010: Design, Automation and Test in Europe. Dresden: European Design and Automation Association, 2010. s. 1731-1736. ISBN: 978-3-9810801-6-2.
  Detail | WWW

  SALVADOR, R.; MORENO, F.; RIESGO, T.; SEKANINA, L. Evolutionary design and optimization of Wavelet Transforms for image compression in embedded systems. Proc. of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2010. s. 177-184. ISBN: 978-1-4244-5888-2.
  Detail

  SEKANINA, L. Evoluční návrh elektronických obvodů. Automa, 2010, roč. 2010, č. 1, s. 48-51. ISSN: 1210-9592.
  Detail | WWW

  SALVADOR, R.; MORENO, F.; RIESGO, T.; SEKANINA, L. Implementation of bio-inspired adaptive wavelet transforms in FPGAs. Modelling, validation and profiling of the algorithm. Proceedings of the XXV Conference on Design of Circuits and Integrated Systems. Lanzarote: The Universidad de Las Palmas de Gran Canaria, 2010. s. 210-215. ISBN: 978-84-693-7393-4.
  Detail

  GAJDA, Z.; SEKANINA, L. An Efficient Selection Strategy for Digital Circuit Evolution. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2010. s. 13-24. ISBN: 978-3-642-15322-8.
  Detail | WWW

  ŠIMÁČEK, J.; SEKANINA, L.; STAREČEK, L. Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2010. s. 214-225. ISBN: 978-3-642-15322-8.
  Detail | WWW

  ŽALOUDEK, L.; SEKANINA, L.; ŠIMEK, V. Accelerating Cellular Automata Evolution on Graphics Processing Units. International Journal on Advances in Software, 2010, roč. 3, č. 1, s. 294-303. ISSN: 1942-2628.
  Detail | WWW

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Towards Scalable and Accurate Microscopic Traffic Simulation Using Advanced Cellular Automata Based Models. Proceedings of the 13th International IEEE Conference on Intelligent Transportation Systems Workshops. Madeira Island: IEEE Intelligent Transportation Systems Society, 2010. s. 27-35. ISBN: 978-972-8822-20-0.
  Detail

  VAŠÍČEK, Z.; SEKANINA, L. Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units. Computing and Informatics, 2010, roč. 29, č. 6, s. 1359-1371. ISSN: 1335-9150.
  Detail | WWW

  GAJDA, Z.; SEKANINA, L. When Does Cartesian Genetic Programming Minimize the Phenotype Size Implicitly?. Proceeding of Genetic and Evolutionary Computation Conference, GECCO 2010. New York: Association for Computing Machinery, 2010. s. 983-984. ISBN: 978-1-4503-0072-8.
  Detail

  FIŠER, P.; SCHMIDT, J.; VAŠÍČEK, Z.; SEKANINA, L. On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming. Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010. s. 346-351. ISBN: 978-1-4244-6610-8.
  Detail | WWW

  ŠIMEK, V.; RŮŽIČKA, R.; SEKANINA, L. On Analysis of Fabricated Polymorphic Circuits. Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010. s. 281-284. ISBN: 978-1-4244-6610-8.
  Detail

  BIDLO, M.; SEKANINA, L. On Impact of Environment on the Complexity Generated by Evolutionary Development. In MENDEL 2010 - 16th International Conference on Soft Computing. Brno: Faculty of Mechanical Engineering BUT, 2010. s. 501-508. ISBN: 978-80-214-4120-0.
  Detail | WWW

  SEKANINA, L. Evoluční návrh hardware. In Umelá inteligencia a kognitívna veda II. Edícia výskumných textov FIIT STU. Bratislava: Vydavateľstvo STU, 2010. s. 437-465. ISBN: 978-80-227-3284-0.
  Detail | WWW

• 2009

  ŠVENDA, P.; SEKANINA, L.; MATYÁŠ, V. Evolutionary Design of Secrecy Amplification Protocols for Wireless Sensor Networks. Proc. of the ACM Conference on Wireless Network Security. New York: Association for Computing Machinery, 2009. s. 225-236. ISBN: 978-1-60558-460-7.
  Detail | WWW

  NEGOITA, M.; SEKANINA, L.; STOICA, A. Adaptive and evolvable hardware and systems: the state of the art and the prospectus for future development. Journal of Automation, Mobile Robotics and Intelligent Systems, 2009, roč. 3, č. 2, s. 70-75. ISSN: 1897-8649.
  Detail

  SEKANINA, L.; RŮŽIČKA, R.; GAJDA, Z. Polymorphic FIR Filters with Backup Mode Enabling Power Savings. Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009. s. 43-50. ISBN: 978-0-7695-3714-6.
  Detail | WWW

  SEKANINA, L. Evolvable Hardware: From Applications to Implications for the Theory of Computation. Proc. of the 8th Int. Conference on Unconventional Computation. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2009. s. 24-36. ISBN: 978-3-642-03744-3.
  Detail | WWW

  VAŠÍČEK, Z.; SEKANINA, L. Efficient Hardware Accelerator for Symbolic Regression Problems. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2009. s. 192-199. ISBN: 978-80-87342-04-6.
  Detail | WWW

  SEKANINA, L.; RŮŽIČKA, R.; VAŠÍČEK, Z.; PROKOP, R.; FUJCIK, L. REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware. Proc. of the 2009 IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware. Nashville: IEEE Computational Intelligence Society, 2009. s. 39-46. ISBN: 978-1-4244-2755-0.
  Detail | WWW

  GAJDA, Z.; SEKANINA, L. Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming. Proc. of 2009 IEEE Congress on Evolutionary Computation. NA: IEEE Computational Intelligence Society, 2009. s. 1599-1604. ISBN: 978-1-4244-2958-5.
  Detail | WWW

  VAŠÍČEK, Z.; BIDLO, M.; SEKANINA, L.; TORRESEN, J.; GLETTE, K.; FURUHOLMEN, M. Evolution of Impulse Bursts Noise Filters. Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009. s. 27-34. ISBN: 978-0-7695-3714-6.
  Detail | WWW

  ŽALOUDEK, L.; SEKANINA, L.; ŠIMEK, V. GPU Accelerators for Evolvable Cellular Automata. Computation World: Future Computing, Service Computation, Adaptive, Content, Cognitive, Patterns. Athens: Institute of Electrical and Electronics Engineers, 2009. s. 533-537. ISBN: 978-0-7695-3862-4.
  Detail

  SEKANINA, L.; VAŠÍČEK, Z.; RŮŽIČKA, R.; BIDLO, M.; JAROŠ, J.; ŠVENDA, P. Evoluční hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojům. Edice Gerstner. Edice Gerstner. Praha: Nakladatelství Academia, 2009. 328 s. ISBN: 978-80-200-1729-1.
  Detail

• 2008

  SEKANINA, L.; STAREČEK, L.; KOTÁSEK, Z.; GAJDA, Z. Polymorphic Gates in Design and Test of Digital Circuits. International Journal of Unconventional Computing, 2008, roč. 4, č. 2, s. 125-142. ISSN: 1548-7199.
  Detail | WWW

  SEKANINA, L.; MIKUŠEK, P. Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures. Applications of Evolutionary Computing. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. s. 144-153. ISBN: 978-3-540-78760-0.
  Detail | WWW

  HORNBY, G.; SEKANINA, L.; HADDOW, P. Proceedings of Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. s. 0-0. ISBN: 978-3-540-85856-0.
  Detail | WWW

  NEGOITA, M.; SEKANINA, L.; STOICA, A. Adaptive and Evolvable Hardware and Systems: The State of the Art and the Prospectus for Future Development. Knowledge-Based Intelligent Information and Engineering Systems. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. s. 310-318. ISBN: 978-3-540-85566-8.
  Detail

  VAŠÍČEK, Z.; SEKANINA, L. Hardware Accelerators for Cartesian Genetic Programming. Eleventh European Conference on Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. s. 230-241. ISBN: 978-3-540-78670-2.
  Detail | WWW

  RŮŽIČKA, R.; SEKANINA, L.; PROKOP, R. Physical Demonstration of Polymorphic Self-checking Circuits. Proc. of the 14th IEEE Int. On-Line Testing Symposium. Los Alamitos: IEEE Computer Society, 2008. s. 31-36. ISBN: 978-0-7695-3264-6.
  Detail | WWW

  VAŠÍČEK, Z.; SEKANINA, L. Novel Hardware Implementation of Adaptive Median Filters. In Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008. s. 110-115. ISBN: 978-1-4244-2276-0.
  Detail | WWW

  VAŠÍČEK, Z.; ČAPKA, L.; SEKANINA, L. Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. Proc. of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2008. s. 3-10. ISBN: 978-0-7695-3166-3.
  Detail | WWW

  PEČENKA, T.; SEKANINA, L.; KOTÁSEK, Z. Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2008, roč. 13, č. 3, s. 1-21. ISSN: 1084-4309.
  Detail | WWW

  VAŠÍČEK, Z.; ŽÁDNÍK, M.; SEKANINA, L.; TOBOLA, J. On Evolutionary Synthesis of Linear Transforms. Evolvable Systems: From Biology > to > Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. s. 141-152. ISBN: 978-3-540-85856-0.
  Detail | WWW

  ŽALOUDEK, L.; SEKANINA, L. Transistor-level Evolution of Digital Circuits Using a Special Circuit Simulator. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. s. 320-331. ISBN: 978-3-540-85856-0.
  Detail | WWW

  STAREČEK, L.; SEKANINA, L.; KOTÁSEK, Z. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008. s. 255-258. ISBN: 978-1-4244-2276-0.
  Detail | WWW

• 2007

  SEKANINA, L. Design and Analysis of a New Self- Testing Adder Which Utilizes Polymorphic Gates. In 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Gliwice: IEEE Computer Society, 2007. s. 243-246. ISBN: 1424411610.
  Detail

  SEKANINA, L. Vztah mezi abstraktním a fyzickým výpočtem v kontextu evolučního návrhu. In Kognice a umělý život VII. Opava: Slezská univerzita v Opavě, 2007. s. 305-310. ISBN: 9788072484126.
  Detail

  SEKANINA, L. Evolvable hardware: Tutorial. In 2007 Genetic and Evolutionary Computational Conference. New York: Association for Computing Machinery, 2007. s. 3627-3644. ISBN: 9781595936981.
  Detail

  SEKANINA, L. Evolutionary Functional Recovery in Virtual Reconfigurable Circuits. ACM Journal on Emerging Technologies in Computing Systems, 2007, roč. 3, č. 2, s. 1-22. ISSN: 1550- 4832.
  Detail

  SEKANINA, L. Evolution of Polymorphic Self- Checking Circuits. In Evolvable Systems: From Biology to Hardware. LNCS 4684. Berlin: Springer Verlag, 2007. s. 186-197. ISBN: 978-3-540-74625- 6.
  Detail

  SEKANINA, L. Evolved Computing Devices and the Implementation Problem. MINDS AND MACHINES, 2007, roč. 17, č. 3, s. 311-329. ISSN: 0924- 6495.
  Detail

  STAREČEK, L.; SEKANINA, L.; GAJDA, Z.; KOTÁSEK, Z.; PROKOP, R.; MUSIL, V. On Properties and Utilization of Some Polymorphic Gates. In 6th Electronic Circuits and Systems Conference (ECS 2007). Bratislava: Faculty of Informatics and Information Technology STU, 2007. s. 77-81. ISBN: 978-80-227-2697- 9.
  Detail

  SLANÝ, K.; SEKANINA, L. Fitness Landscape Analysis and Image Filter Evolution Using Functional- Level CGP. In Genetic Programming, 10th European Conference, EuroGP 2007. Lecture Notes in Computer Science, 4445. Berlin: Springer Verlag, 2007. s. 311-320. ISBN: 978-3-540-71602- 0.
  Detail

  VAŠÍČEK, Z.; SEKANINA, L. An Evolvable Hardware System in Xilinx Virtex II Pro FPGA. International Journal of Innovative Computing and Applications, 2007, roč. 1, č. 1, s. 63-73. ISSN: 1751- 648X.
  Detail

  GAJDA, Z.; SEKANINA, L. Reducing the Number of Transistors in Digital Circuits Using Gate- Level Evolutionary Design. In 2007 Genetic and Evolutionary Computation Conference. New York: Association for Computing Machinery, 2007. s. 245-252. ISBN: 9781595936974.
  Detail

  VAŠÍČEK, Z.; SEKANINA, L. Evaluation of a New Platform For Image Filter Evolution. In Proc. of the 2007 NASA/ ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2007. s. 577-584. ISBN: 076952866X.
  Detail

  VAŠÍČEK, Z.; SEKANINA, L. An Area- Efficient Alternative to Adaptive Median Filtering in FPGAs. In Proc. of 2007 International Conference on Field Programmable Logic and Applications. Los Alamitos: IEEE Computer Society, 2007. s. 216-221. ISBN: 1424410606.
  Detail

  VAŠÍČEK, Z.; SEKANINA, L. Reducing the Area on a Chip Using a Bank of Evolved Filters. In Evolvable Systems: From Biology to Hardware. LNCS 4684. Berlin: Springer Verlag, 2007. s. 222-232. ISBN: 978-3-540-74625- 6.
  Detail

  SEKANINA, L.; MARTÍNEK, T. Evolving Image Operators Directly in Hardware. In Genetic and Evolutionary Computation for Image Processing and Analysis. EURASIP Book Series on Signal Processing and Communications, Volume 8. New York: Hindawi Publishing Corporation, 2007. s. 93-112. ISBN: 978-977-454-001- 1.
  Detail

• 2006

  SEKANINA, L.; VAŠÍČEK, Z. On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. In Applications of Evolutionary Computing. LNCS 3907. Berlin: Springer Verlag, 2006. s. 344-355. ISBN: 978-3-540-33237- 4.
  Detail

  SEKANINA, L.; STAREČEK, L.; KOTÁSEK, Z. Novel Logic Circuits Controlled by Vdd. In Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. s. 85-86. ISBN: 1424401844.
  Detail

  SEKANINA, L. On Dependability of FPGA- Based Evolvable Hardware Systems That Utilize Virtual Reconfigurable Circuits. In Computing Frontiers 2006 Conference. New York: Association for Computing Machinery, 2006. s. 221-228. ISBN: 1595933026.
  Detail

  SEKANINA, L. Evolutionary Design of Digital Circuits: Where Are Current Limits?. In Proc. of the 1st NASA/ ESA Conference on Adaptive Hardware and Systems. Piscataway: IEEE Computer Society, 2006. s. 171-178. ISBN: 0-7695-2614- 4.
  Detail

  SEKANINA, L.; STAREČEK, L.; GAJDA, Z.; KOTÁSEK, Z. Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. In Proc. of the 1st NASA/ ESA Conference on Adaptive Hardware and Systems. Piscataway: IEEE Computer Society, 2006. s. 186-193. ISBN: 0-7695-2614- 4.
  Detail

  RŮŽIČKA, R.; SEKANINA, L. Evolutionary Circuit Design in REPOMO - Reconfigurable Polymorphic Module. In Proceedings of the Second IASTED International Conference on Computational Intelligence. Anaheim: ACTA Press, 2006. s. 237-241. ISBN: 0-88986-602- 3.
  Detail

  ZEBULUM, R.; KEYMEULEN, D.; RAMESHAM, R.; SEKANINA, L.; MAO, J.; KUMAR, N.; STOICA, A. Characterization and Synthesis of Circuits at Extreme Low Temperatures. In Evolvable Hardware. Genetic and Evolutionary Computation. Berlin: Springer Verlag, 2006. s. 161-172. ISBN: 0-387-24386- 0.
  Detail

  PEČENKA, T.; KOTÁSEK, Z.; SEKANINA, L. FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties. In Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. s. 285-289. ISBN: 1424401844.
  Detail

  BIDLO, M.; SEKANINA, L. Prostředky pro podporu vzdělávání v oblasti biologií inspirovaných výpočetních systémů. In Pedagogický software 2006. České Budějovice: Scientifik Pedagogical Publishing, 2006. s. 81-83. ISBN: 80-85645-56- 4.
  Detail

  PEČENKA, T.; STRNADEL, J.; KOTÁSEK, Z.; SEKANINA, L. Testability Estimation Based on Controllability and Observability Parameters. In Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06). IEEE CS. Cavtat: IEEE Computer Society, 2006. s. 504-514. ISBN: 0-7695-2609- 8.
  Detail

  BIDLO, M.; BIDLO, R.; SEKANINA, L. Designing a Novel General Sorting Network Constructor Using Artificial Evolution. Transactions on Engineering, Computing and Technology, 2006, roč. 15, č. 10, s. 85-90. ISSN: 1305- 5313.
  Detail

  SEKANINA, L.; MARTÍNEK, T.; GAJDA, Z. Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules. In 2006 IEEE World Congress on Computational Intelligence. CA: IEEE Computational Intelligence Society, 2006. s. 9676-9683. ISBN: 0-7803-9489- 5.
  Detail

• 2005

  SEKANINA, L. Evoluční design poráží řešení vytvořená kreativním návrhářem. Vesmír, 2005, roč. 84, č. 1, s. 44-46. ISSN: 0042- 4544.
  Detail | WWW

  SEKANINA, L. Evolutionary Design of Gate- Level Polymorphic Digital Circuits. In Applications of Evolutionary Computation. LNCS 3449. Berlin: Springer Verlag, 2005. s. 185-194. ISBN: 978-3-540-25396- 9.
  Detail | WWW

  SEKANINA, L., BIDLO, M. Evolutionary Design of Arbitrarily Large Sorting Networks Using Development. Genetic Programming and Evolvable Machines, 2005, roč. 6, č. 3, s. 319-347. ISSN: 1389- 2576.
  Detail | WWW

  SEKANINA, L. Design Methods for Polymorphic Digital Circuits. In Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. s. 145-150. ISBN: 9639364487.
  Detail | WWW

  SEKANINA, L., ZEBULUM, R. Evolutionary discovering of the concept of the discrete state at the transistor level. In Proc. of the 2005 NASA/ DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005. s. 73-78. ISBN: 0-7695-2399- 4.
  Detail | WWW

  STRNADEL, J., PEČENKA, T., SEKANINA, L. On Testability Analysis Driven Generation of Synthetic Register- Transfer Level Benchmark Circuits. In Proceedings of 5th Electronic Circuits and Systems Conference. Bratislava: Slovak University of Technology in Bratislava, 2005. s. 107-110.
  Detail

  SEKANINA, L., ZEBULUM, R. Intrinsic Evolution of Controllable Oscillators in FPTA- 2. In Evolvable Systems: From Biology to Hardware. Berlin: Springer Verlag, 2005. s. 98-107. ISBN: 978-3-540-28736- 0.
  Detail | WWW

  BIDLO, M., SEKANINA, L. Providing Information from the Environment for Growing Electronic Circuits Through Polymorphic Gates. In Proc. of Genetic and Evolutionary Computation Conference - Workshops 2005. New York: Association for Computing Machinery, 2005. s. 242-248. ISBN: 1-59593-097- 3.
  Detail | WWW

  PEČENKA, T., KOTÁSEK, Z., SEKANINA, L., STRNADEL, J. Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. In Proc. of the 2005 NASA/ DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005. s. 51-58. ISBN: 0-7695-2399- 4.
  Detail | WWW

  MARTÍNEK, T., SEKANINA, L. An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA. In Evolvable Systems: From Biology to Hardware. LNCS 3637. Berlin: Springer Verlag, 2005. s. 76-85. ISBN: 978-3-540-28736- 0.
  Detail | WWW

  KOŘENEK, J., SEKANINA, L. Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. In Evolvable Systems: From Biology to Hardware. LNCS 3637. Berlin: Springer Verlag, 2005. s. 46-55. ISBN: 978-3-540-28736- 0.
  Detail | WWW

  ZEBULUM, R., STOICA, A., KEYMEULEN, D., SEKANINA, L. Evolvable Hardware System at Extreme Low Temperatures. In Evolvable Systems: From Biology to Hardware. LNCS 3637. Berlin: Springer Verlag, 2005. s. 37-45. ISBN: 978-3-540-28736- 0.
  Detail | WWW

• 2004

  SEKANINA, L. Evolving Constructors for Infinitely Growing Sorting Networks and Medians. Lecture Notes in Computer Science, 2004, roč. 2004, č. 2932, s. 314-323. ISSN: 0302-9743.
  Detail | WWW

  KOTÁSEK, Z., PEČENKA, T., STRNADEL, J., MIKA, D., SEKANINA, L. An Overview of Research Activities in Digital Circuit Diagnosis and Benchmarking. In Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004. Košice: The University of Technology Košice, 2004. s. 229-234. ISBN: 80-8073-150- 0.
  Detail | WWW

  SEKANINA, L., DRÁBEK, V. Theory and Applications of Evolvable Embedded Systems. In Proc. of the 11th IEEE Int. Conference and Workshop on the Engineering of Computer- Based Systems. Los Alamitos, CA: IEEE Computer Society Press, 2004. s. 186-193. ISBN: 0-7695-2125- 8.
  Detail | WWW

  SEKANINA, L., FRIEDL, Š. On Routine Implementation of Virtual Evolvable Devices Using COMBO6. In Proc. of the 2004 NASA/ DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2004. s. 63-70. ISBN: 0-7695-2145- 2.
  Detail | WWW

  SEKANINA, L. Evolvable computing by means of evolvable components. Natural Computing, 2004, roč. 3, č. 3, s. 323-355. ISSN: 15677818.
  Detail | WWW

  TORRESEN, J., BAKKE, J., SEKANINA, L. Recognizing Speed Limit Sign Numbers by Evolvable Hardware. Lecture Notes in Computer Science, 2004, roč. 2004, č. 3242, s. 682-691. ISSN: 0302- 9743.
  Detail | WWW

  TORRESEN, J., BAKKE, J., SEKANINA, L. Efficient Recognition of Speed Limit Signs. In Proc. of the 7th International IEEE Conference on Intelligent Transportation Systems. Los Alamos: IEEE Computer Society Press, 2004. s. 1-5. ISBN: 0-7803-8501- 2.
  Detail | WWW

  TORRESEN, J., BAKKE, J., SEKANINA, L. Efficient Image Filtering and Information Reduction in Reconfigurable Logic. In Proc. of 2004 Norchip conference. Oslo: IEEE Computer Society Press, 2004. s. 63-66. ISBN: 0-7803-8510- 1.
  Detail | WWW

  SEKANINA, L., FRIEDL, Š. An Evolvable Combinational Unit for FPGAs. Computing and Informatics, 2004, roč. 23, č. 5, s. 461-486. ISSN: 1335- 9150.
  Detail | WWW

  VAŠÍČEK, Z., SEKANINA, L. Evoluční návrh kombinačních obvodů. Elektrorevue - Internetový časopis (http://www.elektrorevue.cz), 2004, roč. 2004, č. 43, ISSN: 1213- 1539.
  Detail | WWW

  FRIEDL, Š.; SEKANINA, L. The First Circuits Evolved in a Physical Virtual Reconfigurable Device. Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Bratislava: Slovak Academy of Science, 2004. s. 35-42. ISBN: 80-969117-9-1.
  Detail

  PEČENKA, T., KOTÁSEK, Z., SEKANINA, L., STRNADEL, J. Evolutionary Design of Synthetic RTL Benchmark Circuits. In Informal Digest of Papers, IEEE European Test Workshop 2004. Montpellier: IEEE Computer Society, 2004. s. 107-108. ISBN: 000000000.
  Detail | WWW

  VAŠÍČEK, Z., SEKANINA, L. Evoluční návrh kombinačních obvodů. Elektrorevue - Internetový časopis (http://www.elektrorevue.cz), 2004, roč. 2004, č. 43, s. 1-6. ISSN: 1213- 1539.
  Detail | WWW

  RŮŽIČKA, R., SEKANINA, L. A Platform for Demonstration of Analogue and Digital Circuits Evolution. In Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004. Košice: The University of Technology Košice, 2004. s. 158-163. ISBN: 80-8073-150- 0.
  Detail

  SEKANINA, L. Evolutionary Design Space Exploration for Median Circuits. Lecture Notes in Computer Science, 2004, roč. 2004, č. 3005, s. 240-249. ISSN: 0302-9743.
  Detail | WWW

• 2003

  SEKANINA, L. Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. Lecture Notes in Computer Science, 2003, roč. 2003, č. 2606, s. 186-197. ISSN: 0302-9743.
  Detail | WWW

  SEKANINA, L. From Implementations to a General Concept of Evolvable Machines. Lecture Notes in Computer Science, 2003, roč. 2003, č. 2610, s. 424-433. ISSN: 0302-9743.
  Detail | WWW

  SEKANINA, L.; RŮŽIČKA, R. On the Automatic Design of Testable Circuits. Proceedings of IEEE Workshop on Design nad Diagnostics of Electronic Circuits and Systems. Poznań: Publishing House of Poznan University of Technology, 2003. s. 299-300. ISBN: 83-7143-557-6.
  Detail

  RŮŽIČKA, R.; KOTÁSEK, Z.; SEKANINA, L. Sborník pracovního semináře "Počítačové architektury a diagnostika" pro studenty doktorského studia. Brno: Ústav počítačových systémů FIT VUT v Brně, 2003. s. 0-0. ISBN: 80-214-2471-0.
  Detail

  SEKANINA, L.; RŮŽIČKA, R. Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. The 2003 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2003. s. 135-144. ISBN: 0-7695-1977-6.
  Detail | WWW

  SEKANINA, L. Evolvable Components - From Theory to Hardware Implementations. Natural Computing Series. Natural Computing Series. Berlin: Springer Verlag, 2003. 194 s. ISBN: 3-540-40377-9.
  Detail | WWW

  SEKANINA, L. Towards Evolvable IP Cores for FPGAs. Proc. of The 2003 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2003. s. 145-154. ISBN: 0-7695-1977-6.
  Detail | WWW

• 2002

  SEKANINA, L. Image Filter Design with Evolvable Hardware. Lecture Notes in Computer Science, 2002, roč. 2002, č. 2279, s. 255-266. ISSN: 0302-9743.
  Detail | WWW

  SEKANINA, L.; DRÁBEK, V. Automatic Design of Image Operators Using Evolvable Hardware. Proc. of 5th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Brno: Brno University of Technology, 2002. s. 132-139. ISBN: 80-214-2094-4.
  Detail | WWW

  SEKANINA, L. Evolution of digital circuits operating as image filters in dynamically changing environment. Mendel 2002 - 8th International Conference on Soft Computing. Brno: Brno University of Technology, 2002. s. 33-38. ISBN: 80-214-2135-5.
  Detail | WWW

  SEKANINA, L.; TORRESEN, J. Detection of Norwegian Speed Limit Signs. Proc. of the 16th European Simulation Multiconference. Delft: SCS Publication House, 2002. s. 337-340. ISBN: 90-77039-07-4.
  Detail | WWW

  SEKANINA, L. Evolvable Computational Machines: Formal Approach. Intelligent Technologies - Theory and Applications, E-ISCI 2002. Frontiers in Artificial Intelligence and Applications. Amsterdam: IOS Press, 2002. s. 166-172. ISBN: 1-58603-256-9.
  Detail | WWW

  SEKANINA, L.; DRÁBEK, V. Soft-hardware. Vesmír, 2002, roč. 81, č. 7, s. 393-395. ISSN: 0042-4544.
  Detail | WWW

  SLLAME, A.; SEKANINA, L. An Evolutionary-Based Algorithm to the Module Selection Problem with Resource Sharing in High-Level Synthesis. Advances in Nature-Inspired Computation: The PPSN VII Workshops. Reading: PEDAL, Department of Computer Science, University of Reading, 2002. s. 45-46. ISBN: 0-9543481-0-9.
  Detail

  SEKANINA, L.; DRÁBEK, V. A Survey of Bioinspired Methods for Design of Fault Tolerant Reconfigurable Architectures. Proc. of the 8th Biennial Baltic Electronics Conference. Tallinn: Tallinn University of Technology, 2002. s. 355-358. ISBN: 9985-59-292-1.
  Detail

  SEKANINA, L. Nanostructures and bio-inspired computer engineering. Proceedings of Nano02. Ostrava: Repronis, 2002. s. 233-236. ISBN: 80-7329-027-8.
  Detail

  SEKANINA, L. Automata of Evolvable Computational Machines. Proc. ot 8th conference Student EEICT. Brno: Brno University of Technology, 2002. s. 491-495. ISBN: 80-214-2116-9.
  Detail | WWW

  SEKANINA, L. Component Approach to Evolvable Systems. Brno: 2002. s. 0-0.
  Detail

  SLLAME, A.; SEKANINA, L. An Evolutionary-Based Algorithm to the Module Selection Process in High-Level Synthesis. Mendel 2002 - 8th International Conference on Soft Computing. Brno: Brno University of Technology, 2002. s. 87-92. ISBN: 80-214-2135-5.
  Detail | WWW

  DRÁBEK, V.; SEKANINA, L. Basic Principles of Bio-Inspired Approaches to Fault Tolerance: Tutorial. Design for Test of Systems on Chip: Digital Test. Tallinn: Tallinn University of Technology, 2002. s. 1-48. ISBN: 0000-00-000-0.
  Detail

  SEKANINA, L. Nanostructures and bio-inspired computer engineering (Abstract). Nano'02 (Abstracts). Brno: Akademické nakladatelství CERM, 2002. s. 74-74. ISBN: 80-7204-258-0.
  Detail

• 2001

  SEKANINA, L.; DVOŘÁK, V. A Totally Distributed Genetic Algorithm: From a Cellular System to the Mesh of Processors. Modelling and Simulation 2001. Prague: Faculty of Electrical Engineering, Czech Technical University, 2001. s. 539-543. ISBN: 1-56555-225-3.
  Detail | WWW

• 2000

  SEKANINA, L.; DRÁBEK, V. Relation Between Fault Tolerance and Reconfiguration in Cellular Systems. 6th IEEE Int. On-Line Testing Workshop. Palma de Mallorca, Spain: IEEE Computer Society Press, 2000. s. 25-30. ISBN: 0-7695-0646-1.
  Detail | WWW

  SEKANINA, L.; DRÁBEK, V. Fault Tolerance and Reconfiguration in Cellular Systems. Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000. s. 134-137. ISBN: 80-968320-3-4.
  Detail

  SEKANINA, L.; RŮŽIČKA, R. Design of the Special Fast Reconfigurable Chip Using Common FPGA. Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000. s. 161-168. ISBN: 80-968320-3-4.
  Detail | WWW

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