Vysoké učení technické v Brně - Vnitřní projekty VUT

- plně financující (2014-01-01 - 2015-12-31)

FIT-S-14-2297

čeština

Sekanina Lukáš, prof. Ing., Ph.D. - hlavní řešitel
Bartoš Václav, Ing., Ph.D. - spoluřešitel
Bidlo Michal, doc. Ing., Ph.D. - spoluřešitel
Crha Adam, Ing., Ph.D. - spoluřešitel
Čekan Ondřej, Ing., Ph.D. - spoluřešitel
Dobai Roland, Ing., Ph.D. - spoluřešitel
Drábek Vladimír, doc. Ing., CSc. - spoluřešitel
Drahošová Michaela, Ing., Ph.D. - spoluřešitel
Dvořák Milan, Ing. - spoluřešitel
Dvořák Václav, prof. Ing., DrSc. - spoluřešitel
Fučík Otto, doc. Dr. Ing. - spoluřešitel
Hrbáček Radek, Ing., Ph.D. - spoluřešitel
Hyrš Martin, Ing., Ph.D. - spoluřešitel
Jaroš Jiří, doc. Ing., Ph.D. - spoluřešitel
Kadlček Filip, Ing., Ph.D. - spoluřešitel
Kekely Lukáš, Ing., Ph.D. - spoluřešitel
Kořenek Jan, doc. Ing., Ph.D. - spoluřešitel
Košař Vlastimil, Ing., Ph.D. - spoluřešitel
Kováčik Michal, Ing. - spoluřešitel
Martínek Tomáš, doc. Ing., Ph.D. - spoluřešitel
Matoušek Jiří, Ing., Ph.D. - spoluřešitel
Mičulka Lukáš, Ing., Ph.D. - spoluřešitel
Minařík Miloš, Ing., Ph.D. - spoluřešitel
Petrlík Jiří, Ing., Ph.D. - spoluřešitel
Podivínský Jakub, Ing., Ph.D. - spoluřešitel
Růžička Richard, doc. Ing., Ph.D., MBA - spoluřešitel
Schwarz Josef, doc. Ing., CSc. - spoluřešitel
Strnadel Josef, Ing., Ph.D. - spoluřešitel
Szurman Karel, Ing., Ph.D. - spoluřešitel
Šimek Václav, Ing. - spoluřešitel
Tesař Radek, Ing. - spoluřešitel
Tříska Vít, Ing. - spoluřešitel
Vašíček Zdeněk, doc. Ing., Ph.D. - spoluřešitel
Viktorin Jan, Ing. - spoluřešitel
Zachariášová Marcela, Ing., Ph.D. - spoluřešitel
Zamba Martin, Ing. - spoluřešitel
Záň Drahoslav, Ing. - spoluřešitel

Ústav počítačových systémů
- interní (01.01.2014 - 31.12.2016)
Fakulta informačních technologií
- příjemce (01.01.2014 - 31.12.2016)

ZÁŇ, D.; JAROŠ, J. Solving Multidimensional Knapsack Problem using CUDA Accelerated PSO. In Proceedings of the 2014 IEEE Congress on Evolutionary Computation, CEC 2014. Beijing: IEEE Computational Intelligence Society, 2014. p. 2933-2939. ISBN: 978-1-4799-1488-3.
Detail

MINAŘÍK, M.; SEKANINA, L. Exploring the Search Space of Hardware / Software Embedded Systems by Means of GP. In Genetic Programming, 17th European Conference, EuroGP 2014. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2014. p. 112-123. ISBN: 978-3-662-44302-6.
Detail

VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Design of Approximate Multipliers Under Different Error Metrics. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warsaw: IEEE Computer Society, 2014. p. 135-140. ISBN: 978-1-4799-4558-0.
Detail

KOŠAŘ, V.; KOŘENEK, J. On NFA-Split Architecture Optimizations. In 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Warsaw: IEEE Computer Society, 2014. p. 274-277. ISBN: 978-1-4799-4558-0.
Detail

ŠIMEK, V.; RŮŽIČKA, R.; CRHA, A.; TESAŘ, R. Implementation of a Cellular Automaton with Globally Switchable Rules. In 11th International Conference on Cellular Automata for Research and Industry, ACRI 2014. Lecture Notes in Computer Science. Cham: Springer Science+Business Media B.V., 2014. p. 378-387. ISBN: 978-3-319-11519-1.
Detail

TESAŘ, R.; ŠIMEK, V.; RŮŽIČKA, R.; CRHA, A. Polymorphic Electronics Based on Ambipolar OFETs. EDS 2014 IMAPS CS International Conference Proceedings. Brno: Brno University of Technology, 2014. p. 106-111. ISBN: 978-80-214-4985-5.
Detail

JAROŠ, J.; TYRALA, R. GPU-accelerated Evolutionary Design of the Complete Exchange Communication on Wormhole Networks. In GECCO 2014 - Proceedings of the 2014 Genetic and Evolutionary Computation Conference. New York, NY: Association for Computing Machinery, 2014. p. 1023-1030. ISBN: 978-1-4503-2662-9.
Detail

KOTÁSEK, Z.; MIČULKA, L. Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. p. 171-174. ISBN: 978-0-7695-5074-9.
Detail

PETRLÍK, J.; FUČÍK, O.; SEKANINA, L. Multiobjective Selection of Input Sensors for SVR Applied to Road Traffic Prediction. In Parallel Problem Solving from Nature - PPSN XIII. Lecture Notes in Computer Science. Heidelberg: Springer Verlag, 2014. p. 802-811. ISBN: 978-3-319-10761-5.
Detail

STRNADEL, J.; CONTE, G. Producing Unique Identifiers and Random Numbers on Basis of Unclonable Parameters of Microcontrollers and Undesired Effects. Proceedings of Electronic Devices and Systems IMAPS CS International Conference 2014. Brno: Brno University of Technology, 2014. p. 82-87. ISBN: 978-80-214-4985-5.
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STRNADEL, J.; POKORNÝ, M. Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. In Proceedings of the 2014 17th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2014. p. 333-340. ISBN: 978-1-4799-5793-4.
Detail

ŠIMEK, V.; RŮŽIČKA, R. Reconfigurable Platform with Polymorphic Digital Gates and Partial Reconfiguration Feature. In Proceedings on UKSim-AMSS 8th European Modelling Symposium on Mathematical Modelling and Computer Simulation. Pisa: IEEE Computer Society, 2014. p. 501-506. ISBN: 978-1-4799-7411-5.
Detail

ZÁVODNÍK, T.; KEKELY, L.; PUŠ, V. CRC based hashing in FPGA using DSP blocks. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. p. 179-182. ISBN: 978-1-4799-4558-0.
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KEKELY, L.; ŽÁDNÍK, M.; MATOUŠEK, J.; KOŘENEK, J. Fast Lookup for Dynamic Packet Filtering in FPGA. In Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014. Warszawa: IEEE Computer Society, 2014. p. 219-222. ISBN: 978-1-4799-4558-0.
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PUŠ, V.; KEKELY, L.; KOŘENEK, J. Design Methodology of Configurable High Performance Packet Parser for FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. p. 189-194. ISBN: 978-1-4799-4558-0.
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DVOŘÁK, M.; KOŘENEK, J. Low Latency Book Handling in FPGA for High Frequency Trading. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. p. 175-178. ISBN: 978-1-4799-4558-0.
Detail

ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Solving of Constraint Satisfaction Problem. Proceedings of the 20th Conference STUDENT EEICT 2014. Volume 3. Brno: Faculty of Information Technology BUT, 2014. p. 291-295. ISBN: 978-80-214-4924-4.
Detail

DRAHOŠOVÁ, M.; KOMJÁTHY, G.; SEKANINA, L. Towards Compositional Coevolution in Evolutionary Circuit Design. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 157-164. ISBN: 978-1-4799-4479-8.
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KEKELY, L.; PUŠ, V.; KOŘENEK, J. Software Defined Monitoring of Application Protocols. In Proceedings of IEEE INFOCOM 2014 - IEEE Conference on Computer Communications. Toronto: IEEE Computer Society, 2014. p. 1725-1733. ISBN: 978-1-4799-3360-0.
Detail

PODIVÍNSKÝ, J. Testing Fault-Tolerance Properties in FPGA based Electro-mechanical Applications. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. p. 13-18. ISBN: 978-80-7494-027-9.
Detail

VIKTORIN, J. Využití dynamické rekonfigurace vestavěných systémů pro monitorování počítačových sítí. Počítačové architektury a diagnostika 2014. Liberec: Technická univerzita v Liberci, 2014. s. 50-55. ISBN: 978-80-7494-027-9.
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PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 312-319. ISBN: 978-1-4799-5793-4.
Detail

KEKELY, L. Software Defined Monitoring: Nový prístup k monitorovaniu vysokorýchlostných počítačových sietí. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. s. 74-79. ISBN: 978-80-7494-027-9.
Detail

HYRŠ, M.; SCHWARZ, J. Estimation of distribution algorithm with copula probabilistic model:a short introduction. In Proceedings of 20th international conference of softcomputing. Brno: Faculty of Mechanical Engineering BUT, 2014. p. 71-76. ISBN: 978-80-214-4984-8.
Detail

PETRLÍK, J.; FUČÍK, O.; SEKANINA, L. Multiobjective Selection of Input Sensors for Travel Times Forecasting Using Support Vector Regression. In 2014 IEEE Symposium on Computational Intelligence in Vehicles and Transportation Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 14-21. ISBN: 978-1-4799-4498-9.
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VIKTORIN, J.; KORČEK, P.; KOŘENEK, J.; FUKAČ, T. Network monitoring probe based on Xilinx Zynq. In Proceedings of the 2012 Tenth ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2014). Marina del Rey, CA, USA: Association for Computing Machinery, 2014. p. 237-238. ISBN: 978-1-4503-2839-5.
Detail

KOŠAŘ, V.; KOŘENEK, J. Multi-Stride NFA-Split Architecture for Regular Expression Matching Using FPGA. Proceedings of the 9th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: NOVPRESS s.r.o., 2014. p. 77-88. ISBN: 978-80-214-5022-6.
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SZURMAN, K.; MIČULKA, L.; KOTÁSEK, Z. State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 704-707. ISBN: 978-1-4799-5793-4.
Detail

SZURMAN, K. Synchronization Methodology for Fault Tolerant System Recovery After Its Failure. Počítačové architektury & diagnostika 2014. Malá Skála: Liberec University of Technology, 2014. p. 111-116. ISBN: 978-80-7494-027-9.
Detail

KEKELY, L.; PUŠ, V.; BENÁČEK, P.; KOŘENEK, J. Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring. In 2014 24th International Conference on Field Programmable Logic and Applications (FPL 2014). Munich: IEEE Circuits and Systems Society, 2014. p. 264-267. ISBN: 978-3-00-044645-0.
Detail

TESAŘ, R.; RŮŽIČKA, R.; ŠIMEK, V. Resistant Gates for Polymorphic Electronics. In Proceedings on UKSim-AMSS 8th European Modelling Symposium on Mathematical Modelling and Computer Simulation. Pisa: IEEE Computer Society, 2014. p. 513-518. ISBN: 978-1-4799-7412-2.
Detail

MRÁZEK, V. Akcelerace evolučního návrhu digitálních obvodů na úrovni tranzistorů s využitím platformy Zynq. Proceedings of the 20th Student Conference, EEICT 2014. Volume 2. Brno: Vysoké učení technické v Brně, 2014. s. 229-231. ISBN: 978-80-214-4923-7.
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ZACHARIÁŠOVÁ, M. Application of Evolutionary Computing for Optimization of Functional Verification. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. p. 135-140. ISBN: 978-80-7494-027-9.
Detail

ČEKAN, O. Universal Generation of Test Vectors for Functional Verification. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014. p. 44-49. ISBN: 978-80-7494-027-9.
Detail

HYRŠ, M.; SCHWARZ, J. Multivariate Gaussian Copula in Estimation of Distribution Algorithm with Model Migration. In 2014 IEEE Symposium on Foundations of Computational Intelligence (FOCI) Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 114-119. ISBN: 978-1-4799-4492-7.
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SZURMAN, K.; MIČULKA, L.; KOTÁSEK, Z. Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems. In 9th IEEE International Conference on Computer Engineering and Systems. Káhira: IEEE Computer Society, 2014. p. 231-236. ISBN: 978-1-4799-6594-6.
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STRNADEL, J.; SLIMAŘÍK, F. Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems. Computing and Informatics, 2014, vol. 33, no. 4, p. 757-782. ISSN: 1335-9150.
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DOBAI, R.; SEKANINA, L. Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware. ACM Transactions on Reconfigurable Technology and Systems, 2015, vol. 8, no. 3, p. 1-24. ISSN: 1936-7406.
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SEKANINA, L. Principles and Applications of Polymorphic Circuits. In Evolvable Hardware - From Practice to Application. Berlin: Springer Verlag, 2015. p. 209-224. ISBN: 978-3-662-44615-7.
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VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Approach to Approximate Digital Circuits Design. IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, 2015, vol. 19, no. 3, p. 432-444. ISSN: 1089-778X.
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MATOUŠEK, J. Analýza dynamických vlastností směrovacích tabulek pro efektivnější implementaci směrování v páteřních sítích. Sborník příspěvků PAD-2014 - elektronická verze. Liberec: Technická univerzita v Liberci, 2014. s. 129-134. ISBN: 978-80-7494-027-9.
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GROCHOL, D.; SEKANINA, L.; ŽÁDNÍK, M.; KOŘENEK, J. A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. In Applications of Evolutionary Computation, 18th European Conference. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. p. 67-78. ISBN: 978-3-319-16548-6.
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DRAHOŠOVÁ, M.; HULVA, J.; SEKANINA, L. Indirectly Encoded Fitness Predictors Coevolved with Cartesian Programs. In Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. p. 113-125. ISBN: 978-3-319-16500-4.
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BARTOŠ, V. Using Application-Aware Flow Monitoring for SIP Fraud Detection. In Intelligent Mechanisms for Network Configuration and Security. Lecture Notes in Computer Science. Ghent: Springer International Publishing, 2015. p. 87-99. ISBN: 978-3-319-20033-0.
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STRNADEL, J. Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads. In Proceedings of the 2015 4th Eastern European Regional Conference on the Engineering of Computer Based Systems. Brno: Brno University of Technology, 2015. p. 39-44. ISBN: 978-1-4673-7967-0.
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KOŠAŘ, V.; KOŘENEK, J. Towards Efficient Field Programmeable Pattern Matching Array. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 1-8. ISBN: 978-1-4673-8035-5.
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PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; ČEKAN, O.; KOTÁSEK, Z. FPGA Prototyping and Accelerated Verification of ASIPs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. p. 145-148. ISBN: 978-1-4799-6780-3.
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PETRLÍK, J.; SEKANINA, L. Towards Robust and Accurate Traffic Prediction Using Parallel Multiobjective Genetic Algorithms and Support Vector Regression. In 2015 IEEE 18th International Conference on Intelligent Transportation Systems. Los Alamitos: IEEE Computer Society, 2015. p. 2231-2236. ISBN: 978-1-4673-6596-3.
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KEKELYOVÁ, M.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z.; HRUŠKA, T. Application of Evolutionary Algorithms for Optimization of Regression Suites. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. p. 91-94. ISBN: 978-1-4799-6779-7.
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MRÁZEK, V. Evoluční návrh nízkopříkonových obvodů. Počítačové architektury a diagnostika PAD 2015. Zlín: Fakulta aplikované informatiky, Univerzita Tomáše Bati ve Zlíně, 2015. s. 1-6. ISBN: 978-80-7454-522-1.
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TOMAN, J.; HRBÁČEK, R.; SINGULE, V. Redundant Control Algorithm for a Brushless DC Motor. In EDPE 2015 Proceedings of the 18th International Conference on Electrical Drives and Power Electronics. Košice: The University of Technology Košice, 2015. p. 117-123. ISBN: 978-1-4673-7376-0.
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KRČMA, M.; KAŠTIL, J.; KOTÁSEK, Z. Mapping trained neural networks to FPNNs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. p. 157-160. ISBN: 978-1-4799-6779-7.
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JAROŠ, J.; MAREK, J.; MENŠÍK, P. Optimisation of Water Management Systems Using a GPU-Accelerated Differential Evolution. In Proceedings - 2015 IEEE Symposium Series on Computational Intelligence, SSCI 2015. Cape Town: IEEE Computer Society, 2015. p. 1727-1734. ISBN: 978-1-4799-7560-0.
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KEKELY, L.; KUČERA, J.; PUŠ, V.; KOŘENEK, J.; VASILAKOS, A. Software Defined Monitoring of Application Protocols. IEEE TRANSACTIONS ON COMPUTERS, 2015, vol. 65, no. 2, p. 615-626. ISSN: 0018-9340.
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ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Automation and Optimization of Coverage-driven Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 87-94. ISBN: 978-1-4673-8035-5.
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ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Software Fault Tolerance: the Evaluation by Functional Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 284-287. ISBN: 978-1-4673-8035-5.
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SLANÝ, K. Cartesian Genetic Programming in a Changing Environment. In Proceedings of the 7th International Joint Conference on Computational Intelligence (IJCCI 2015). Lisbon: SciTePress - Science and Technology Publications, 2015. p. 204-211. ISBN: 978-989-758-157-1.
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ČEKAN, O. Principy generování verifikačních stimulů. Počítačové architektury a diagnostika PAD 2015. Zlín: Fakulta aplikované informatiky, Univerzita Tomáše Bati ve Zlíně, 2015. s. 13-18. ISBN: 978-80-7454-522-1.
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KRČMA, M.; KOTÁSEK, Z.; KAŠTIL, J. Fault Tolerant Field Programmable Neural Networks. In 1st IEEE Nordic Circuits and Systems (NORCAS) Conference. Oslo: IEEE Computer Society, 2015. p. 1-4. ISBN: 978-1-4673-6575-8.
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KRČMA, M. FPNN - neuronové sítě v FPGA. Počítačové architektury a diagnostika PAD 2015. Zlín: Univerzita Tomáše Bati ve Zlíně, 2015. s. 81-86. ISBN: 978-80-7454-522-1.
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HYRŠ, M.; SCHWARZ, J. Elliptical and Archimedean Copulas in Estimation of Distribution Algorithm. In MENDEL 2015 21st International Conference on Soft Computing. Brno: Faculty of Mechanical Engineering BUT, 2015. p. 19-26. ISBN: 978-80-214-4984-8.
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HYRŠ, M.; SCHWARZ, J. Elliptical and Archimedean Copulas in Estimation of Distribution Algorithm with Model Migration. In Proceedings of the 7th International Joint Conference on Computational Intelligence (IJCCI 2015). Lisbon: SciTePress - Science and Technology Publications, 2015. p. 212-219. ISBN: 978-989-758-157-1.
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PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. Microprocessors and Microsystems, 2015, vol. 39, no. 8, p. 1215-1230. ISSN: 0141-9331.
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ŠIMEK, V.; RŮŽIČKA, R.; CRHA, A. Toward Efficient Synthesis Method of Multifunctional Logic Circuits. In Proceedings of the 27th International Conference on Microelectronics (ICM 2015). Casablanca: IEEE Computer Society, 2015. p. 21-24. ISBN: 978-1-4673-8759-0.
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NIKL, V. High Performance Computing on Low Power Devices. Počítačové architektury a diagnostika 2015. Zlín: Faculty of Applied Informatics, Tomas Bata University in Zlín, 2015. p. 37-41. ISBN: 978-80-7454-522-1.
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BARTOŠ, V.; KOŘENEK, J. Evaluating Reputation of Internet Entities. In Management and Security in the Age of Hyperconnectivity. Lecture Notes in Computer Science. Munich: Springer International Publishing, 2016. p. 132-136. ISBN: 978-3-319-39813-6.
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STRNADEL, J. Modeling and Analysis of Fault-Tolerant Systems by Means of UPPAAL SMC: Method and Benefits. Informal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Bratislava: Slovak University of Technology in Bratislava, 2016. p. 32-37. ISBN: 978-80-8086-256-5.
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HRBÁČEK, R.; MRÁZEK, V.; VAŠÍČEK, Z. Automatic Design of Approximate Circuits by Means of Multi-Objective Evolutionary Algorithms. In Proceedings of the 11th International Conference on Design & Technology of Integrated Systems in Nanoscale Era. Istanbul: Istanbul Sehir University, 2016. p. 239-244. ISBN: 978-1-5090-0335-8.
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SEKANINA, L.; KAPUSTA, V. Visualisation and Analysis of Genetic Records Produced by Cartesian Genetic Programming. In GECCO'16 Companion. New York: Association for Computing Machinery, 2016. p. 1411-1418. ISBN: 978-1-4503-4323-7.
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PODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; KOTÁSEK, Z. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. In Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016. p. 487-494. ISBN: 978-1-5090-2816-0.
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ZACHARIÁŠOVÁ, M.; KEKELYOVÁ, M.; KOTÁSEK, Z. Regression Test Suites Optimization for Application-specific Instruction-set Processors and Their Use for Dependability Analysis. In Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol Cyprus: IEEE Computer Society, 2016. p. 380-387. ISBN: 978-1-5090-2816-0.
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KRČMA, M.; KOTÁSEK, Z.; LOJDA, J.; KAŠTIL, J. Comparsion of FPNNs models approximation capabilities and resources utilization. Proceedings of the Work in progress Session held in connection with DSD 2016. Limassol: Johannes Kepler University Linz, 2016. p. 1-2. ISBN: 978-3-902457-46-2.
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KOŠAŘ, V.; KOŘENEK, J. Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA. In Proceedings of The 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016. p. 591-598. ISBN: 978-1-5090-2816-0.
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KOŘENEK, J.; VIKTORIN, J. Packet Processing on FPGA SoC with DPDK. In 26th International Conference on Field-Programmable Logic and Applications. Lausanne: École Polytechnique Fédérale de Lausanne, 2016. p. 578-579. ISBN: 978-2-8399-1844-2.
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RIŠA, M. Scheduling and Synchronization on Multicores. Sborník příspěvků Česko-slovenského semináře pro studenty doktorského studia Počítačové architektury & diagnostika. Brno: Faculty of Information Technology BUT, 2016. p. 10-13. ISBN: 978-80-214-5376-0.
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PODIVÍNSKÝ, J. Funkční verifikace jako nástroj pro sledování vlivu poruch na elektro-mechanický systém. Počítačové architektury a diagnostika PAD 2016. Bořetice - Kraví Hora: Fakulta informačních technologií VUT v Brně, 2016. s. 101-104. ISBN: 978-80-214-5376-0.
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ČEKAN, O. Generování testovacích stimulů. Počítačové architektury a diagnostika PAD 2016. Bořetice - Kraví Hora: Fakulta informačních technologií VUT v Brně, 2016. s. 97-100. ISBN: 978-80-214-5376-0.
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VAVERKA, F. Case Study on Multi-domain Decomposition of k-Wave Simulation Framework. Computer achitectures and diagnostics 2016. Brno: Faculty of Information Technology BUT, 2016. p. 37-40. ISBN: 978-80-214-5376-0.
Detail

NIKL, V. High Performance Computing on Low Power Devices. Computer achitectures and diagnostics 2016. Brno: Faculty of Information Technology BUT, 2016. p. 81-84. ISBN: 978-80-214-5376-0.
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STRNADEL, J.; RIŠA, M. On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC. In Proceedings of the 24th Austrian Workshop on Microelectronics. Villach: IEEE Computer Society Press, 2016. p. 45-50. ISBN: 978-1-5090-1040-0.
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PODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; KOTÁSEK, Z. Functional Verification as a Tool for Monitoring Impact of Faults in SRAM-based FPGAs. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. p. 293-294. ISBN: 978-1-5090-5602-6.
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ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Random Stimuli Generation Based on a Stochastic Context-Free Grammar. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. p. 295-296. ISBN: 978-1-5090-5602-6.
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LOJDA, J.; PODIVÍNSKÝ, J.; KRČMA, M.; KOTÁSEK, Z. HLS-based Fault Tolerance Approach for SRAM-based FPGAs. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. p. 301-302. ISBN: 978-1-5090-5602-6.
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ŠIMEK, V.; TESAŘ, R.; RŮŽIČKA, R.; CRHA, A. Modelling and Physical Implementation of Ambipolar Components Based on Organic Materials. In Proceedings of the 28th International Conference on Microelectronics (ICM 2016). Cairo: IEEE Circuits and Systems Society, 2016. p. 341-344. ISBN: 978-1-5090-5721-4.
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MRÁZEK, V.; VAŠÍČEK, Z. Automatic Design of Arbitrary-Size Approximate Sorting Networks with Error Guarantee. In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016 26rd International Workshop on. Bremen: Institute of Electrical and Electronics Engineers, 2016. p. 221-228. ISBN: 978-1-5090-0733-2.
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MRÁZEK, V. Evoluční snižování příkonu: Od obvodů na úrovni tranzistorů po neuronové sítě na čipu. Počítačové architektury a diagnostika PAD 2016. Bořetice: Fakulta informačních technologií VUT v Brně, 2016. s. 61-64. ISBN: 978-80-214-5376-0.
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HYRŠ, M.; SCHWARZ, J. Kopulové EDA algoritmy. Počítačové architektury & diagnostika PAD 2016. Bořetice: Fakulta informačních technologií VUT v Brně, 2016. s. 105-108. ISBN: 978-80-214-5376-0.
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GROCHOL, D. Evoluční hardware v síťových aplikacích. Počítačové architektury a diagnostika PAD 2016. Bořetice: Fakulta informačních technologií VUT v Brně, 2016. s. 57-60. ISBN: 978-80-214-5376-0.
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HYRŠ, M.; SCHWARZ, J. Advanced Parallel Copula Based EDA. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016. p. 1-8. ISBN: 978-1-5090-4239-5.
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MATOUŠEK, D.; KOŘENEK, J.; PUŠ, V. High-speed Regular Expression Matching with Pipelined Automata. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. p. 93-100. ISBN: 978-1-5090-5602-6.
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GROCHOL, D.; SEKANINA, L. Comparison of Parallel Linear Genetic Programming Implementations. In Recent Advances in Soft Computing: Proceedings of the 22nd International Conference on Soft Computing (MENDEL 2016) held in Brno, Czech Republic, at June 8-10, 2016. Cham: Springer International Publishing, 2017. p. 64-76. ISBN: 978-3-319-58088-3.
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NIKL, V.; HRADECKÝ, M.; JAROŠ, J.; KELEČÉNI, J. The investigation of the ARMv7 and Intel Haswell architectures suitability for performance and energy-aware computing. In High Performance Computing. Lecture Notes in Computer Science. Cham: Springer International Publishing, 2017. p. 377-393. ISBN: 978-3-319-58666-3.
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ČEKAN, O.; KOTÁSEK, Z. Random Test Stimuli Generation Based on a Probabilistic Grammar. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017. p. 43-44. ISBN: 978-80-01-06178-7.
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MATOUŠEK, J. Addressing Issues in Research on Packet Classification in Core Networks. Brno: Faculty of Information Technology BUT, 2019. p. 0-0.
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GROEN, D.; CHACRA, D.; NASH, R.; JAROŠ, J.; BERNABEU, M.; COVENEY, P. Weighted decomposition in high-performance lattice-Boltzmann simulations: are some lattice sites more equal than others?. In Solving Software Challengesfor Exascale. Lecture Notes in Computer Science. Stockholm: Springer Verlag, 2015. p. 28-38. ISBN: 978-3-319-15975-1.
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ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Universal Pseudo-random Generation of Assembler Codes for Processors. Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015. p. 70-73.
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PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Radiation Impact on Mechanical Application Driven by FPGA-based Controller. Proceedings of The Fourth Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015. p. 13-16.
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ČEKAN, O.; KOTÁSEK, Z. Software-implemented Fault-Tolerant Program Generation. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016. p. 13-13. ISBN: 978-80-01-05984-5.
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SZURMAN, K.; MIČULKA, L.; KOTÁSEK, Z. Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016. p. 0-0. ISBN: 978-80-01-05984-5.
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KOTÁSEK, Z.; PODIVÍNSKÝ, J. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016. p. 0-0.
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